Re: [PATCH] drm/i915: Add HSW CRT output readout support

Daniel Vetter
2013-09-24T10:55:36Z

On Tue, Sep 24, 2013 at 01:47:21PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Call intel_ddi_get_config() to get the pipe_bpp settings from
> DDI.
>
> The sync polarity settings from DDI are irrelevant for CRT
> output, so override them with data from the ADPA register.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69691
> Tested-by: Qingshuai Tian <qingshuai.tian@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 33 ++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index f9a5f3d..ca7fd09 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -113,6 +113,34 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
> pipe_config->adjusted_mode.clock = dotclock;
> }
>
> +static void hsw_crt_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_crt *crt = intel_encoder_to_crt(encoder);
> + u32 tmp, flags = 0;
> +
> + intel_ddi_get_config(encoder, pipe_config);
> +
> + tmp = I915_READ(crt->adpa_reg);
> +
> + if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NHSYNC;
> +
> + if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NVSYNC;

Can't we reuse that a bit by extracing a get_flags helper form
intel_crt_get_config? There's a bit of clock readout still in there, but
that can wait until later ...
-Daniel

> +
> + pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> + DRM_MODE_FLAG_NHSYNC |
> + DRM_MODE_FLAG_PVSYNC |
> + DRM_MODE_FLAG_NVSYNC);
> + pipe_config->adjusted_mode.flags |= flags;
> +}
> +
> /* Note: The caller is required to filter out dpms modes not supported by the
> * platform. */
> static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> @@ -804,7 +832,10 @@ void intel_crt_init(struct drm_device *dev)
> crt->base.mode_set = intel_crt_mode_set;
> crt->base.disable = intel_disable_crt;
> crt->base.enable = intel_enable_crt;
> - crt->base.get_config = intel_crt_get_config;
> + if (IS_HASWELL(dev))
> + crt->base.get_config = hsw_crt_get_config;
> + else
> + crt->base.get_config = intel_crt_get_config;
> if (I915_HAS_HOTPLUG(dev))
> crt->base.hpd_pin = HPD_CRT;
> if (HAS_DDI(dev))
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7e9fa53..a43ac3a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1269,8 +1269,8 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
> intel_dp_check_link_status(intel_dp);
> }
>
> -static void intel_ddi_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_config *pipe_config)
> +void intel_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fb38ef1..e7fe5f1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -828,5 +828,7 @@ extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe
>
> extern bool intel_crtc_active(struct drm_crtc *crtc);
> extern void i915_disable_vga_mem(struct drm_device *dev);
> +extern void intel_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 1.8.1.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch