From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 3/5] drm/i915/vlv: warn on bad VLV PLL
 divider values
Date: Fri, 27 Sep 2013 13:17:29 -0700
Message-ID: <20130927131729.203c49db@jbarnes-desktop>
References: <1380311846-1581-1-git-send-email-jbarnes@virtuousgeek.org>
	<1380311846-1581-3-git-send-email-jbarnes@virtuousgeek.org>
	<20130927200524.GC744@nuc-i3427.alporthouse.com>
	<20130927201133.GJ26592@phenom.ffwll.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from oproxy7-pub.mail.unifiedlayer.com
	(oproxy7-pub.mail.unifiedlayer.com [67.222.55.9])
	by gabe.freedesktop.org (Postfix) with SMTP id 7B8EBE5BFA
	for <intel-gfx@lists.freedesktop.org>;
	Fri, 27 Sep 2013 13:17:23 -0700 (PDT)
In-Reply-To: <20130927201133.GJ26592@phenom.ffwll.local>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, 27 Sep 2013 22:11:33 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, Sep 27, 2013 at 09:05:24PM +0100, Chris Wilson wrote:
> > On Fri, Sep 27, 2013 at 12:57:24PM -0700, Jesse Barnes wrote:
> > > This avoids a divide by zero and warns appropriately on this serious bug.
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 8da1c96..9a83236 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5109,6 +5109,11 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> > >  	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
> > >  	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
> > >  
> > > +	if (!clock.n || !(clock.p1 * clock.p2)) {
> > 
> > if ((clock.n & clock.p1 & clock.p2) == 0) {
> > 
> > or just
> > 
> > if (!clock.n || !clock.p1 || !clock.p2)
> > 
> > > +		WARN(1, "bad divider values on pipe %d\n", crtc->pipe);
> > > +		return;
> > > +	}
> > > +
> > 
> > So I think you want
> > 
> > if (WARN_ONCE(clock.n == 0 || clock.p1 == 0 || clock.p2 == 0,
> >               "bad divider values on pipe %d (m1=%d, m2=%d, p1=%d, p2=%d, n=%d)\n",
> > 	      crtc->pipe, clock.m1, clock.m2, clock.p1, clock.p2, clock.n))
> >    return;
> 
> So the bios leaves a broken setup behind or is our hw state readout not
> quite careful enough?

No this just happens when we're really broken.  E.g. we don't set the
integrated clock bit and then try to enable a PLL and fail all over.

Shouldn't happen in practice.

-- 
Jesse Barnes, Intel Open Source Technology Center