From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: intel_pre_enable_dp
Date: Sun, 29 Sep 2013 17:16:58 -0700
Message-ID: <20130929171658.6eab2b61@jbarnes-desktop>
References: <20130929234813.GU18242@two.firstfloor.org>
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To: Andi Kleen <andi@firstfloor.org>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Mon, 30 Sep 2013 01:53:47 +0200
Andi Kleen <andi@firstfloor.org> wrote:

> On Mon, Sep 30, 2013 at 01:48:13AM +0200, Andi Kleen wrote:
> > 
> > Jesse,
> > 
> > I was playing with a static analyzer and it flagged the following
> > code of yours.
> > 
> > Is the val = 0 directly after the register read correct and intended?
> 
> Also the same pattern is in other places, like vlv_pre_enable_dp.

Hm definitely looks suspect... I'll check it out.  On the plus side
that code is actually working in practice, so maybe the zeroing isn't
too harmful. :)

-- 
Jesse Barnes, Intel Open Source Technology Center