From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround
Date: Tue, 1 Oct 2013 21:24:49 +0200 [thread overview]
Message-ID: <20131001192449.GW26592@phenom.ffwll.local> (raw)
In-Reply-To: <1379704879-1635-1-git-send-email-przanoni@gmail.com>
On Fri, Sep 20, 2013 at 04:21:19PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This workaround is described in the mode set sequence documentation.
> When enabling planes for the second pipe, we need to wait for 2
> vblanks on the first pipe. This should solve "a flash of screen
> corruption if planes are enabled on second/third pipe during the time
> that big FIFO mode is exiting". Watermarks are fun :)
>
> v2: Save indentation levels
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Last two patches of this series merged to dinq.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-10-01 19:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-19 20:00 [PATCH 0/4] Haswell modeset fixes Paulo Zanoni
2013-09-19 20:00 ` [PATCH 1/4] drm/i915: promote FIFO underruns to DRM_ERROR Paulo Zanoni
2013-09-19 20:16 ` Chris Wilson
2013-09-19 20:20 ` Paulo Zanoni
2013-09-19 20:27 ` Chris Wilson
2013-09-20 6:32 ` Ville Syrjälä
2013-09-20 18:38 ` Paulo Zanoni
2013-09-19 20:00 ` [PATCH 2/4] drm/i915: don't disable ERR_INT on the IRQ handler Paulo Zanoni
2013-09-19 20:18 ` Chris Wilson
2013-09-20 8:08 ` Daniel Vetter
2013-09-19 20:00 ` [PATCH 3/4] drm/i915: Disable/enable planes as the first/last thing during modeset on HSW Paulo Zanoni
2013-09-19 20:00 ` [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround Paulo Zanoni
2013-09-20 6:29 ` Ville Syrjälä
2013-09-20 19:21 ` Paulo Zanoni
2013-10-01 19:24 ` Daniel Vetter [this message]
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