From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations. Date: Wed, 2 Oct 2013 15:31:47 -0700 Message-ID: <20131002223147.GA6580@bwidawsk.net> References: <1380751423-6255-1-git-send-email-currojerez@riseup.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id ADF18E5DF6 for ; Wed, 2 Oct 2013 15:31:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Thu, Oct 03, 2013 at 12:20:43AM +0200, Daniel Vetter wrote: > On Thu, Oct 3, 2013 at 12:03 AM, Francisco Jerez wrote: > > + case I915_PARAM_HAS_ATOMICS: > > + value = 1; > > + break; > > Generally when we do kernel fixes for gpu hangs like that we don't add > parameters (would drown in them otherwise) but simply queue it up to > -fixes and slap a cc: stable on it. Gpu hang fixes are critical enough > imo for that treatment, even when it's for brand new userspace code. > > Any specific reason why we shouldn't follow this approach here? I'd > make the patch simpler and we could dump a bit of userspace code, too. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch They haven't yet enabled this feature in mesa, so it's not exactly fixing a hang. It is preventing one from ever occurring. Mesa versions built against an older libdrm will not use atomics. -- Ben Widawsky, Intel Open Source Technology Center