From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/vlv: Turn off power gate for BIOS-less system. Date: Thu, 3 Oct 2013 19:34:48 +0300 Message-ID: <20131003163447.GY9395@intel.com> References: <1380006867-20771-1-git-send-email-chon.ming.lee@intel.com> <1380813377-5992-1-git-send-email-chon.ming.lee@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 69367E67C7 for ; Thu, 3 Oct 2013 09:34:51 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1380813377-5992-1-git-send-email-chon.ming.lee@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chon Ming Lee Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Oct 03, 2013 at 11:16:17PM +0800, Chon Ming Lee wrote: > During system boot up, by default, the power gate for render, media and > display well still power gated. Normally, BIOS will turn off the power > gate. In the BIOS-less system, the driver need to turn off the power > gate very early during driver load. > = > v2: Move this to intel_uncore_sanitize to allow it to get call during > resume path. (Daniel) > v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of > just 0x1 (Ville) > Add turn of power gate for display 2d/render well/media well. > v4: Remove toggle cmnreset in intel_uncore_sanitize. Cmnreset should > toggle after CRI clock source has been selected. Jesse DPIO reset patch > which toggle the cmnreset in intel_modeset_init_hw() should handle it. > (Ville) > = > Signed-off-by: Chon Ming Lee Looks OK as a short term solution. Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++ > drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++++++++++ > 2 files changed, 25 insertions(+), 0 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 3432de4..f14310b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -361,6 +361,15 @@ > #define PUNIT_OPCODE_REG_READ 6 > #define PUNIT_OPCODE_REG_WRITE 7 > = > +#define PUNIT_REG_PWRGT_CTRL 0x60 > +#define PUNIT_REG_PWRGT_STATUS 0x61 > +#define PUNIT_CLK_GATE 1 > +#define PUNIT_PWR_RESET 2 > +#define PUNIT_PWR_GATE 3 > +#define RENDER_PWRGT (PUNIT_PWR_GATE << 0) > +#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2) > +#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6) > + > #define PUNIT_REG_GPU_LFM 0xd3 > #define PUNIT_REG_GPU_FREQ_REQ 0xd4 > #define PUNIT_REG_GPU_FREQ_STS 0xd8 > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/i= ntel_uncore.c > index f2753d9..288a3a6 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -301,10 +301,26 @@ static void intel_uncore_forcewake_reset(struct drm= _device *dev) > = > void intel_uncore_sanitize(struct drm_device *dev) > { > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + u32 reg_val; > + > intel_uncore_forcewake_reset(dev); > = > /* BIOS often leaves RC6 enabled, but disable it for hw init */ > intel_disable_gt_powersave(dev); > + > + /* Turn off power gate, require especially for the BIOS less system */ > + if (IS_VALLEYVIEW(dev)) { > + > + mutex_lock(&dev_priv->rps.hw_lock); > + reg_val =3D vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); > + > + if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) > + vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); > + > + mutex_unlock(&dev_priv->rps.hw_lock); > + > + } > } > = > /* > -- = > 1.7.7.6 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC