* [PATCH] drm/i915/vlv: reset DPIO on load and resume
@ 2013-09-26 21:39 Jesse Barnes
2013-09-26 21:51 ` Daniel Vetter
2013-09-27 9:34 ` Ville Syrjälä
0 siblings, 2 replies; 7+ messages in thread
From: Jesse Barnes @ 2013-09-26 21:39 UTC (permalink / raw)
To: intel-gfx
This fixes resume on my test platform, since I think some DPIO bits need
recalibration.
References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f52e6d4..320f729 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}
+static void intel_init_dpio(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (!IS_VALLEYVIEW(dev))
+ return;
+
+ /* Reset in case DPIO was stuck across suspend/resume or boot */
+ I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
+}
+
static void vlv_enable_pll(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
{
intel_prepare_ddi(dev);
+ intel_init_dpio(dev);
+
intel_init_clock_gating(dev);
mutex_lock(&dev->struct_mutex);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-09-26 21:39 [PATCH] drm/i915/vlv: reset DPIO on load and resume Jesse Barnes
@ 2013-09-26 21:51 ` Daniel Vetter
2013-09-26 21:58 ` Jesse Barnes
2013-09-27 9:34 ` Ville Syrjälä
1 sibling, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2013-09-26 21:51 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> This fixes resume on my test platform, since I think some DPIO bits need
> recalibration.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f52e6d4..320f729 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> }
>
> +static void intel_init_dpio(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (!IS_VALLEYVIEW(dev))
> + return;
> +
> + /* Reset in case DPIO was stuck across suspend/resume or boot */
> + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
> +}
> +
> static void vlv_enable_pll(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> {
> intel_prepare_ddi(dev);
>
> + intel_init_dpio(dev);
> +
> intel_init_clock_gating(dev);
Can't you just put this into the clock_gate function? I'd like to cut down
a bit on our general clutter in the setup code since tbh I've completely
lost the overview of what goes where ...
-Daniel
>
> mutex_lock(&dev->struct_mutex);
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-09-26 21:51 ` Daniel Vetter
@ 2013-09-26 21:58 ` Jesse Barnes
2013-09-27 6:11 ` Lee, Chon Ming
0 siblings, 1 reply; 7+ messages in thread
From: Jesse Barnes @ 2013-09-26 21:58 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, 26 Sep 2013 23:51:52 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > This fixes resume on my test platform, since I think some DPIO bits need
> > recalibration.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f52e6d4..320f729 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> > }
> >
> > +static void intel_init_dpio(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (!IS_VALLEYVIEW(dev))
> > + return;
> > +
> > + /* Reset in case DPIO was stuck across suspend/resume or boot */
> > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
> > +}
> > +
> > static void vlv_enable_pll(struct intel_crtc *crtc)
> > {
> > struct drm_device *dev = crtc->base.dev;
> > @@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> > {
> > intel_prepare_ddi(dev);
> >
> > + intel_init_dpio(dev);
> > +
> > intel_init_clock_gating(dev);
>
> Can't you just put this into the clock_gate function? I'd like to cut down
> a bit on our general clutter in the setup code since tbh I've completely
> lost the overview of what goes where ...
Seemed more appropriate for modeset code, but of course it could go
anywhere.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-09-26 21:58 ` Jesse Barnes
@ 2013-09-27 6:11 ` Lee, Chon Ming
0 siblings, 0 replies; 7+ messages in thread
From: Lee, Chon Ming @ 2013-09-27 6:11 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On 09/26 14:58, Jesse Barnes wrote:
> On Thu, 26 Sep 2013 23:51:52 +0200
> Daniel Vetter <daniel@ffwll.ch> wrote:
>
> > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > > This fixes resume on my test platform, since I think some DPIO bits need
> > > recalibration.
> > >
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index f52e6d4..320f729 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> > > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> > > }
> > >
> > > +static void intel_init_dpio(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = dev->dev_private;
> > > +
> > > + if (!IS_VALLEYVIEW(dev))
> > > + return;
> > > +
> > > + /* Reset in case DPIO was stuck across suspend/resume or boot */
> > > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
> > > +}
> > > +
> > > static void vlv_enable_pll(struct intel_crtc *crtc)
> > > {
> > > struct drm_device *dev = crtc->base.dev;
> > > @@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> > > {
> > > intel_prepare_ddi(dev);
> > >
> > > + intel_init_dpio(dev);
> > > +
> > > intel_init_clock_gating(dev);
> >
> > Can't you just put this into the clock_gate function? I'd like to cut down
> > a bit on our general clutter in the setup code since tbh I've completely
> > lost the overview of what goes where ...
>
> Seemed more appropriate for modeset code, but of course it could go
> anywhere.
>
The patch below is doing the same thing, but reset in intel_uncore_sanitize.
drm/i915: Send a DPIO cmnreset during driver load or system resume.
Same as Jesse patch, it solves the resume issue also. If usnig Jesse
patch, I will remove the DPIO reset in intel_uncore_sanitize.
> --
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-09-26 21:39 [PATCH] drm/i915/vlv: reset DPIO on load and resume Jesse Barnes
2013-09-26 21:51 ` Daniel Vetter
@ 2013-09-27 9:34 ` Ville Syrjälä
2013-10-03 16:38 ` Ville Syrjälä
1 sibling, 1 reply; 7+ messages in thread
From: Ville Syrjälä @ 2013-09-27 9:34 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> This fixes resume on my test platform, since I think some DPIO bits need
> recalibration.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f52e6d4..320f729 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> }
>
> +static void intel_init_dpio(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (!IS_VALLEYVIEW(dev))
> + return;
> +
> + /* Reset in case DPIO was stuck across suspend/resume or boot */
> + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
This will deassert the common lane reset, so the comment is confusing,
as is the name we have given this bit.
> +}
> +
> static void vlv_enable_pll(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> {
> intel_prepare_ddi(dev);
>
> + intel_init_dpio(dev);
> +
> intel_init_clock_gating(dev);
>
> mutex_lock(&dev->struct_mutex);
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-09-27 9:34 ` Ville Syrjälä
@ 2013-10-03 16:38 ` Ville Syrjälä
2013-10-03 16:46 ` Jesse Barnes
0 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjälä @ 2013-10-03 16:38 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > This fixes resume on my test platform, since I think some DPIO bits need
> > recalibration.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f52e6d4..320f729 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> > }
> >
> > +static void intel_init_dpio(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (!IS_VALLEYVIEW(dev))
> > + return;
> > +
> > + /* Reset in case DPIO was stuck across suspend/resume or boot */
> > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
>
> This will deassert the common lane reset, so the comment is confusing,
> as is the name we have given this bit.
And the commit subject and text is also confusing in the same way.
And we should do this after setting up the CRI clock.
>
> > +}
> > +
> > static void vlv_enable_pll(struct intel_crtc *crtc)
> > {
> > struct drm_device *dev = crtc->base.dev;
> > @@ -10279,6 +10290,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> > {
> > intel_prepare_ddi(dev);
> >
> > + intel_init_dpio(dev);
> > +
> > intel_init_clock_gating(dev);
> >
> > mutex_lock(&dev->struct_mutex);
> > --
> > 1.8.3.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume
2013-10-03 16:38 ` Ville Syrjälä
@ 2013-10-03 16:46 ` Jesse Barnes
0 siblings, 0 replies; 7+ messages in thread
From: Jesse Barnes @ 2013-10-03 16:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 3 Oct 2013 19:38:26 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > > This fixes resume on my test platform, since I think some DPIO bits need
> > > recalibration.
> > >
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index f52e6d4..320f729 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> > > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> > > }
> > >
> > > +static void intel_init_dpio(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = dev->dev_private;
> > > +
> > > + if (!IS_VALLEYVIEW(dev))
> > > + return;
> > > +
> > > + /* Reset in case DPIO was stuck across suspend/resume or boot */
> > > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET);
> >
> > This will deassert the common lane reset, so the comment is confusing,
> > as is the name we have given this bit.
>
> And the commit subject and text is also confusing in the same way.
>
> And we should do this after setting up the CRI clock.
So I'm still confused by this. The bit is called "CMNRST", which
doesn't say anything to me about deasserting common lane reset, unless
you mean setting it to 0, which the docs imply. But here we're setting
it to on 1. But I guess you're talking about something than the other
gunit register HAS?
At any rate, it's not confusing to me now, though it may become so if I
try to read a few more docs...
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-10-03 16:55 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2013-09-26 21:39 [PATCH] drm/i915/vlv: reset DPIO on load and resume Jesse Barnes
2013-09-26 21:51 ` Daniel Vetter
2013-09-26 21:58 ` Jesse Barnes
2013-09-27 6:11 ` Lee, Chon Ming
2013-09-27 9:34 ` Ville Syrjälä
2013-10-03 16:38 ` Ville Syrjälä
2013-10-03 16:46 ` Jesse Barnes
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