Re: [PATCH] drm/i915/vlv: reset DPIO on load and resume v2

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Oct 03, 2013 at 11:35:46AM -0700, Jesse Barnes wrote:
> DPIO needs to have common reset de-asserted on soft resets like boot and
> S3.  In some cases, the BIOS will have done this for us, but it should
> be safe to do at runtime as well, as long as we do it when the pipes are
> otherwise off.
> 
> v2: update bit name to match docs better (Ville)
>     reset after CRI clock select (Ville)
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++++++++
>  2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ba263d7..ffa5b52 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -430,7 +430,7 @@
>  #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
>  #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
>  #define  DPIO_SFR_BYPASS		(1<<1)
> -#define  DPIO_RESET			(1<<0)
> +#define  DPIO_CMNRST			(1<<0)
>  
>  #define _DPIO_TX3_SWING_CTL4_A		0x690
>  #define _DPIO_TX3_SWING_CTL4_B		0x2a90
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9cba743..972f842 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1360,6 +1360,26 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
>  }
>  
> +static void intel_init_dpio(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	if (!IS_VALLEYVIEW(dev))
> +		return;
> +
> +	/*
> +	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> +	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
> +	 *   a.	GUnit 0x2110 bit[0]  set to 1 (def 0)
> +	 *   b.	The other bits such as sfr settings / modesel may all be set
> +	 *      to 0.
> +	 *
> +	 * This should only be done on init and resume from S3 with both
> +	 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
> +	 */
> +	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
> +}
> +
>  static void vlv_enable_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> @@ -10379,6 +10399,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
>  		I915_WRITE(DPLL(1), I915_READ(DPLL(1)) |
>  			   DPLL_INTEGRATED_CRI_CLK_VLV);
>  
> +	intel_init_dpio(dev);
> +

Since you're adding a new function the cri clock setup could be moved
there as well. But whatever.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	mutex_lock(&dev->struct_mutex);
>  	intel_enable_gt_powersave(dev);
>  	mutex_unlock(&dev->struct_mutex);
> -- 
> 1.8.3.1
> 
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-- 
Ville Syrjälä
Intel OTC
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