From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915/dp: update training set in a burst write with training pattern set Date: Fri, 4 Oct 2013 15:48:03 +0300 Message-ID: <20131004124803.GD9395@intel.com> References: <1380888528-4507-1-git-send-email-jani.nikula@intel.com> <1380888528-4507-2-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 52CE9E5E0B for ; Fri, 4 Oct 2013 05:48:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1380888528-4507-2-git-send-email-jani.nikula@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Oct 04, 2013 at 03:08:48PM +0300, Jani Nikula wrote: > The DP spec allows this, and requires it when full link training is > started with non-minimum voltage swing and/or non-zero pre-emphasis. > = > Signed-off-by: Jani Nikula Looks good. For the series: Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index 0ed7717..bfd0e76 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2314,7 +2314,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, > struct drm_device *dev =3D intel_dig_port->base.base.dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > enum port port =3D intel_dig_port->port; > - int ret; > + uint8_t buf[sizeof(intel_dp->train_set) + 1]; > + int ret, len; > = > if (HAS_DDI(dev)) { > uint32_t temp =3D I915_READ(DP_TP_CTL(port)); > @@ -2384,22 +2385,21 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, > I915_WRITE(intel_dp->output_reg, *DP); > POSTING_READ(intel_dp->output_reg); > = > - ret =3D intel_dp_aux_native_write_1(intel_dp, DP_TRAINING_PATTERN_SET, > - dp_train_pat); > - if (ret !=3D 1) > - return false; > - > - if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=3D > + buf[0] =3D dp_train_pat; > + if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) =3D=3D > DP_TRAINING_PATTERN_DISABLE) { > - ret =3D intel_dp_aux_native_write(intel_dp, > - DP_TRAINING_LANE0_SET, > - intel_dp->train_set, > - intel_dp->lane_count); > - if (ret !=3D intel_dp->lane_count) > - return false; > + /* don't write DP_TRAINING_LANEx_SET on disable */ > + len =3D 1; > + } else { > + /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ > + memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); > + len =3D intel_dp->lane_count + 1; > } > = > - return true; > + ret =3D intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, > + buf, len); > + > + return ret =3D=3D len; > } > = > static bool > -- = > 1.7.9.5 -- = Ville Syrj=E4l=E4 Intel OTC