* [PATCH] drm/i915: Fix VGA_DISP_DISABLE check
@ 2013-10-04 17:32 ville.syrjala
2013-10-04 18:07 ` Jesse Barnes
0 siblings, 1 reply; 3+ messages in thread
From: ville.syrjala @ 2013-10-04 17:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The VGACNTRL register contains a bunch of other stuff besides
the VGA_DISP_DISABLE bit. When we write the register we always set those
other bits to zero, so normally the current check would work.
However on HSW disabling and re-enabling the power well will reset the
VGACNTRL register to its default value, which has several of the other
bits set as well.
So only look at the VGA_DISP_DISABLE bit when checking whether the VGA
plane needs re-disabling.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0ba0af4..925a387 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev)
(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
return;
- if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
+ if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
i915_disable_vga(dev);
i915_disable_vga_mem(dev);
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Fix VGA_DISP_DISABLE check
2013-10-04 17:32 [PATCH] drm/i915: Fix VGA_DISP_DISABLE check ville.syrjala
@ 2013-10-04 18:07 ` Jesse Barnes
2013-10-04 19:06 ` Daniel Vetter
0 siblings, 1 reply; 3+ messages in thread
From: Jesse Barnes @ 2013-10-04 18:07 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Fri, 4 Oct 2013 20:32:25 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The VGACNTRL register contains a bunch of other stuff besides
> the VGA_DISP_DISABLE bit. When we write the register we always set those
> other bits to zero, so normally the current check would work.
>
> However on HSW disabling and re-enabling the power well will reset the
> VGACNTRL register to its default value, which has several of the other
> bits set as well.
>
> So only look at the VGA_DISP_DISABLE bit when checking whether the VGA
> plane needs re-disabling.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0ba0af4..925a387 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev)
> (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
> return;
>
> - if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> i915_disable_vga(dev);
> i915_disable_vga_mem(dev);
Looks good.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Fix VGA_DISP_DISABLE check
2013-10-04 18:07 ` Jesse Barnes
@ 2013-10-04 19:06 ` Daniel Vetter
0 siblings, 0 replies; 3+ messages in thread
From: Daniel Vetter @ 2013-10-04 19:06 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Fri, Oct 04, 2013 at 11:07:19AM -0700, Jesse Barnes wrote:
> On Fri, 4 Oct 2013 20:32:25 +0300
> ville.syrjala@linux.intel.com wrote:
>
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The VGACNTRL register contains a bunch of other stuff besides
> > the VGA_DISP_DISABLE bit. When we write the register we always set those
> > other bits to zero, so normally the current check would work.
> >
> > However on HSW disabling and re-enabling the power well will reset the
> > VGACNTRL register to its default value, which has several of the other
> > bits set as well.
> >
> > So only look at the VGA_DISP_DISABLE bit when checking whether the VGA
> > plane needs re-disabling.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0ba0af4..925a387 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev)
> > (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
> > return;
> >
> > - if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> > + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> > DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> > i915_disable_vga(dev);
> > i915_disable_vga_mem(dev);
>
> Looks good.
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-10-04 18:07 ` Jesse Barnes
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