From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Fix VGA_DISP_DISABLE check Date: Fri, 4 Oct 2013 21:06:24 +0200 Message-ID: <20131004190624.GU31334@phenom.ffwll.local> References: <1380907945-1994-1-git-send-email-ville.syrjala@linux.intel.com> <20131004110719.08ba832e@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by gabe.freedesktop.org (Postfix) with ESMTP id 15BF3E6A23 for ; Fri, 4 Oct 2013 12:06:06 -0700 (PDT) Received: by mail-ea0-f182.google.com with SMTP id o10so1982824eaj.41 for ; Fri, 04 Oct 2013 12:06:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20131004110719.08ba832e@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Oct 04, 2013 at 11:07:19AM -0700, Jesse Barnes wrote: > On Fri, 4 Oct 2013 20:32:25 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > The VGACNTRL register contains a bunch of other stuff besides > > the VGA_DISP_DISABLE bit. When we write the register we always set those > > other bits to zero, so normally the current check would work. > > = > > However on HSW disabling and re-enabling the power well will reset the > > VGACNTRL register to its default value, which has several of the other > > bits set as well. > > = > > So only look at the VGA_DISP_DISABLE bit when checking whether the VGA > > plane needs re-disabling. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 0ba0af4..925a387 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev) > > (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) =3D= =3D 0) > > return; > > = > > - if (I915_READ(vga_reg) !=3D VGA_DISP_DISABLE) { > > + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { > > DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); > > i915_disable_vga(dev); > > i915_disable_vga_mem(dev); > = > Looks good. > = > Reviewed-by: Jesse Barnes Queued for -next, thanks for the patch. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch