From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 7/7] drm/i915: Mark gen specific conditions 'likely' Date: Sat, 5 Oct 2013 14:37:27 +0200 Message-ID: <20131005123727.GV31334@phenom.ffwll.local> References: <1380946975-14431-1-git-send-email-benjamin.widawsky@intel.com> <1380946975-14431-7-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f175.google.com (mail-ea0-f175.google.com [209.85.215.175]) by gabe.freedesktop.org (Postfix) with ESMTP id C31F0E5C5F for ; Sat, 5 Oct 2013 05:37:10 -0700 (PDT) Received: by mail-ea0-f175.google.com with SMTP id m14so2257010eaj.6 for ; Sat, 05 Oct 2013 05:37:09 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1380946975-14431-7-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Fri, Oct 04, 2013 at 09:22:55PM -0700, Ben Widawsky wrote: > Now that MMIO has been split up into gen specific functions it is > obvious when HAS_FPGA_DBG_UNCLAIMED, HAS_FORCE_WAKE are needed. > > I'm a bit on the fence whether or not to even have the checks at all. > For now I am leaving them there because I think they are valuable for > debug, and early silicon bringup. In these cases, one could hardcode the > appropriate values, and not have forcewake, and fpga_dbg. > > Signed-off-by: Ben Widawsky Can't we just completely fold away the gen/platform checks now? -Daniel > --- > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index cd56212..30fbee0 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -307,7 +307,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) > > /* We give fast paths for the really cool registers */ > #define NEEDS_FORCE_WAKE(dev_priv, reg) \ > - ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ > + ((likely(HAS_FORCE_WAKE((dev_priv)->dev))) && \ > ((reg) < 0x40000) && \ > ((reg) != FORCEWAKE)) > > @@ -323,7 +323,7 @@ ilk_dummy_write(struct drm_i915_private *dev_priv) > static void > hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) > { > - if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && > + if (likely(HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev)) && > (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { > DRM_ERROR("Unknown unclaimed register before writing to %x\n", > reg); > @@ -334,7 +334,7 @@ hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) > static void > hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) > { > - if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && > + if (likely(HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev)) && > (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { > DRM_ERROR("Unclaimed write to %x\n", reg); > __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch