From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: wait for IPS_ENABLE when enabling IPS Date: Tue, 8 Oct 2013 23:58:04 +0200 Message-ID: <20131008215804.GH8303@phenom.ffwll.local> References: <1379620986-1702-1-git-send-email-przanoni@gmail.com> <1379620986-1702-3-git-send-email-przanoni@gmail.com> <20130919202433.GC7745@nuc-i3427.alporthouse.com> <20130920081232.GI32145@phenom.ffwll.local> <20130920214900.GM32145@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F156E7584 for ; Tue, 8 Oct 2013 14:57:46 -0700 (PDT) Received: by mail-ee0-f54.google.com with SMTP id e53so4280723eek.41 for ; Tue, 08 Oct 2013 14:57:45 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: Intel Graphics Development , Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Tue, Oct 08, 2013 at 06:02:30PM -0300, Paulo Zanoni wrote: > 2013/9/20 Daniel Vetter : > > On Fri, Sep 20, 2013 at 12:18:29PM -0300, Paulo Zanoni wrote: > >> 2013/9/20 Daniel Vetter : > >> > On Thu, Sep 19, 2013 at 09:24:33PM +0100, Chris Wilson wrote: > >> >> On Thu, Sep 19, 2013 at 05:03:06PM -0300, Paulo Zanoni wrote: > >> >> > From: Paulo Zanoni > >> >> > > >> >> > At the end of haswell_crtc_enable we have an intel_wait_for_vblank > >> >> > with a big comment, and the message suggests it's a workaround for > >> >> > something we don't really understand. So I removed that wait and > >> >> > started getting HW state readout error messages saying that the IPS > >> >> > state is not what we expected. > >> >> > > >> >> > I investigated and concluded that after you write IPS_ENABLE to > >> >> > IPS_CTL, the bit will only actually become 1 on the next vblank. So > >> >> > add code to wait for the IPS_ENABLE bit. We don't really need this > >> >> > wait right now due to the wait I already mentioned, but at least this > >> >> > one has a reason to be there, while the other one is just to > >> >> > workaround some problem: we may remove it in the future. > >> >> > > >> >> > The wait also acts as a POSTING_READ which we missed. > >> >> > > >> >> > Signed-off-by: Paulo Zanoni > >> >> > >> >> Both patches: > >> >> Reviewed-by: Chris Wilson > >> >> > >> >> I was thinking that maybe the intel_wait_for_vblank would be better from > >> >> a documenting perspective - and it would also give warnings for trying > >> >> to enable ips whilst the pipe was off. But you would still need the wait > >> >> for IPS_ENABLE as confirmation anyway. > >> > > >> > Both queued for -next, thanks for the patches&review. > >> > >> Hmmm, this patch depends on the "enable planes only after the pipe is > >> really running" patch. Due to that missing patch, now I get > >> "[drm:hsw_enable_ips] *ERROR* Timed out waiting for IPS enable" when > >> booting. I should have said this, sorry :( > > > > Ok, I've dropped it again. > > It should be safe to merge it now. Done, thanks for the ping. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch