Re: [Intel-gfx] [PATCH 3/4] drm/i915: implement another plane WM workaround for HSW

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Oct 07, 2013 at 05:15:47PM -0300, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> In some Haswell machines we're seeing a full system hang while calling
> haswell_crtc_enable. Ville bisected the problem to the following
> commit:
>     commit 90a8864320b2a9f91e5b5d561924a4bb70b90dcc
>     Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
>     Date:   Fri May 3 17:23:45 2013 -0300
>         drm/i915: set FORCE_ARB_IDLE_PLANES workaround
> 
> After some BSpec-digging I discovered that we don't implement one of
> the workarounds mentioned in the description of bit 31 of PRI_CTL,
> SPR_CTL and CUR_CTL. This patch implements the workaround, which makes
> the problem go away on my machine. Also notice that the workaround
> implementation is almost a revert of the commit mentioned above, but
> it still allows LP watermarks to be used.
> 
> Thanks to Ville for the help debugging the issue and for doing the
> bisect.

You can drop this patch. It's not needed anymore.

> 
> Cc: stable@vger.kernel.org
> Credits-to: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bc47f1e..8069bff 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3565,6 +3565,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> +	uint32_t wm_dbg_val;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -3597,6 +3598,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	intel_ddi_set_pipe_settings(crtc);
>  	intel_ddi_enable_transcoder_func(crtc);
>  
> +	/* Workaround described in PRI_CTL, CUR_CTL and SPR_CTL bit 31. */
> +	wm_dbg_val = I915_READ(WM_DBG);
> +	I915_WRITE(WM_DBG, wm_dbg_val | WM_DBG_DISALLOW_MULTIPLE_LP |
> +			   WM_DBG_DISALLOW_MAXFIFO | WM_DBG_DISALLOW_SPRITE);
> +
>  	intel_update_watermarks(crtc);
>  	intel_enable_pipe(dev_priv, pipe,
>  			  intel_crtc->config.has_pch_encoder, false);
> @@ -3623,6 +3629,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	 * happening.
>  	 */
>  	intel_wait_for_vblank(dev, intel_crtc->pipe);
> +
> +	/* Second part of the WM_DBG workaround. */
> +	I915_WRITE(WM_DBG, wm_dbg_val);
>  }
>  
>  static void ironlake_pfit_disable(struct intel_crtc *crtc)
> -- 
> 1.8.1.4
> 
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-- 
Ville Syrjälä
Intel OTC