From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: Avoid tweaking RPS before it is enabled Date: Thu, 10 Oct 2013 14:06:02 -0700 Message-ID: <20131010140602.734c52d5@jbarnes-desktop> References: <1381438730-23985-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.mail.unifiedlayer.com (oproxy7-pub.mail.unifiedlayer.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id 57073E763D for ; Thu, 10 Oct 2013 14:06:01 -0700 (PDT) In-Reply-To: <1381438730-23985-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 10 Oct 2013 21:58:50 +0100 Chris Wilson wrote: > As we delay the initial RPS enabling (upon boot and after resume), there > is a chance that we may start to render and trigger RPS boosts before we > set up the punit. Any changes we make could result in inconsistent > hardware state, with a danger of causing undefined behaviour. However, > as the boosting is a optional tweak to RPS, we can simply ignore it > whilst RPS is not yet enabled. > > Signed-off-by: Chris Wilson > Cc: Daniel Vetter > Cc: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++---------- > 2 files changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 640bff2..e0152e7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -874,6 +874,7 @@ struct intel_gen6_power_mgmt { > int last_adj; > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > > + bool enabled; > struct delayed_work delayed_resume_work; > > /* > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6ffeb04..8070a07 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3435,22 +3435,26 @@ void gen6_set_rps(struct drm_device *dev, u8 val) > void gen6_rps_idle(struct drm_i915_private *dev_priv) > { > mutex_lock(&dev_priv->rps.hw_lock); > - if (dev_priv->info->is_valleyview) > - valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > - else > - gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > - dev_priv->rps.last_adj = 0; > + if (dev_priv->rps.enabled) { > + if (dev_priv->info->is_valleyview) > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > + else > + gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > + dev_priv->rps.last_adj = 0; > + } > mutex_unlock(&dev_priv->rps.hw_lock); > } > > void gen6_rps_boost(struct drm_i915_private *dev_priv) > { > mutex_lock(&dev_priv->rps.hw_lock); > - if (dev_priv->info->is_valleyview) > - valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay); > - else > - gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay); > - dev_priv->rps.last_adj = 0; > + if (dev_priv->rps.enabled) { > + if (dev_priv->info->is_valleyview) > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay); > + else > + gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay); > + dev_priv->rps.last_adj = 0; > + } > mutex_unlock(&dev_priv->rps.hw_lock); > } > > @@ -4657,6 +4661,7 @@ void intel_disable_gt_powersave(struct drm_device *dev) > valleyview_disable_rps(dev); > else > gen6_disable_rps(dev); > + dev_priv->rps.enabled = false; > mutex_unlock(&dev_priv->rps.hw_lock); > } > } > @@ -4676,6 +4681,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) > gen6_enable_rps(dev); > gen6_update_ring_freq(dev); > } > + dev_priv->rps.enabled = true; > mutex_unlock(&dev_priv->rps.hw_lock); > } > Yeah looks good. Probably better than doing a sync on the delayed work too, since that'll take over 1s. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center