From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [RFC] Runtime display PM for VLV/BYT Date: Tue, 15 Oct 2013 11:06:06 +0300 Message-ID: <20131015080606.GM13047@intel.com> References: <1381792069-27800-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B3036E7FE7 for ; Tue, 15 Oct 2013 01:06:26 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1381792069-27800-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 14, 2013 at 04:07:44PM -0700, Jesse Barnes wrote: > This set adds bits needed for runtime power support, currently only > lightly tested on VLV/BYT: > 1) suspend/resume callbacks for different platforms > 2) save/restore of display state across a power well toggle > 3) get/put of display power well in critical places > = > The TODO list still has a few items on it, and I'm looking for feedback: > 1) sprinkle around some power well WARNs so we can catch things easily > 2) add some tests using DPMS and NULL mode sets and comparing power > well state > 3) better debugfs support for multiple wells > 4) refcount of power well in debugfs (with ref holders?) > 5) more testing - I think the load time ref is still busted here and > on HSW > 6) convert HSW as well so DPMS will shut things down, not just mode > sets > = > Thoughts or comments? I'd also like to see what Imre cooked up, and then come up with some grand unified design. Based on our discussions I think his power well abstraction sounded somewhat nicer and more general. Also your locking seems to be fubar in places (frobbing with sideband while holding a spinlock). I think Imre converted the power wells to use a mutex everywhere. Or perhaps we just start with your stuff and Imre rebases his stuff on top? -- = Ville Syrj=E4l=E4 Intel OTC