From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/2] drm/i915: Make PTE valid encoding optional Date: Fri, 18 Oct 2013 15:40:19 +0200 Message-ID: <20131018134019.GX4830@phenom.ffwll.local> References: <1381940302-1920-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by gabe.freedesktop.org (Postfix) with ESMTP id DCF5AE5F00 for ; Fri, 18 Oct 2013 06:40:01 -0700 (PDT) Received: by mail-ea0-f182.google.com with SMTP id o10so1998940eaj.13 for ; Fri, 18 Oct 2013 06:40:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1381940302-1920-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 16, 2013 at 09:18:21AM -0700, Ben Widawsky wrote: Empty commit messages aren't cool, especially for a fix this late in the -rc cycle. Patches simply need to be justified. I've filled something in when merging. > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/i915_gem_gtt.c | 35 ++++++++++++++++++++--------------- > 2 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 6106d3d..0cbeb0e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -517,7 +517,8 @@ struct i915_address_space { > > /* FIXME: Need a more generic return type */ > gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, > - enum i915_cache_level level); > + enum i915_cache_level level, > + bool valid); /* Create a valid PTE */ > void (*clear_range)(struct i915_address_space *vm, > unsigned int first_entry, > unsigned int num_entries); > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index e999496..81dce29 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -58,9 +58,10 @@ > #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) > > static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, > - enum i915_cache_level level) > + enum i915_cache_level level, > + bool valid) > { > - gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; > pte |= GEN6_PTE_ADDR_ENCODE(addr); > > switch (level) { > @@ -79,9 +80,10 @@ static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, > } > > static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, > - enum i915_cache_level level) > + enum i915_cache_level level, > + bool valid) > { > - gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; > pte |= GEN6_PTE_ADDR_ENCODE(addr); > > switch (level) { > @@ -105,9 +107,10 @@ static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, > #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) > > static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, > - enum i915_cache_level level) > + enum i915_cache_level level, > + bool valid) > { > - gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; > pte |= GEN6_PTE_ADDR_ENCODE(addr); > > /* Mark the page as writeable. Other platforms don't have a > @@ -122,9 +125,10 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, > } > > static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, > - enum i915_cache_level level) > + enum i915_cache_level level, > + bool valid) > { > - gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; > pte |= HSW_PTE_ADDR_ENCODE(addr); > > if (level != I915_CACHE_NONE) > @@ -134,9 +138,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, > } > > static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, > - enum i915_cache_level level) > + enum i915_cache_level level, > + bool valid) > { > - gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; > pte |= HSW_PTE_ADDR_ENCODE(addr); > > switch (level) { > @@ -245,7 +250,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm, > unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; > unsigned last_pte, i; > > - scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); > + scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); > > while (num_entries) { > last_pte = first_pte + num_entries; > @@ -282,7 +287,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, > dma_addr_t page_addr; > > page_addr = sg_page_iter_dma_address(&sg_iter); > - pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level); > + pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); > if (++act_pte == I915_PPGTT_PT_ENTRIES) { > kunmap_atomic(pt_vaddr); > act_pt++; > @@ -536,7 +541,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, > > for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { > addr = sg_page_iter_dma_address(&sg_iter); > - iowrite32(vm->pte_encode(addr, level), >t_entries[i]); > + iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); > i++; > } > > @@ -548,7 +553,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, > */ > if (i != 0) > WARN_ON(readl(>t_entries[i-1]) != > - vm->pte_encode(addr, level)); > + vm->pte_encode(addr, level, true)); > > /* This next bit makes the above posting read even more important. We > * want to flush the TLBs only after we're certain all the PTE updates > @@ -573,7 +578,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm, > first_entry, num_entries, max_entries)) > num_entries = max_entries; > > - scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); > + scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); > for (i = 0; i < num_entries; i++) > iowrite32(scratch_pte, >t_base[i]); > readl(gtt_base); > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch