From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/3] drm/i915: Wire up gen2 CRC support Date: Mon, 21 Oct 2013 13:22:40 +0300 Message-ID: <20131021102240.GS13047@intel.com> References: <1381956961-16875-17-git-send-email-daniel.vetter@ffwll.ch> <1382107027-20521-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 4EB03E6998 for ; Mon, 21 Oct 2013 03:22:44 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1382107027-20521-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, Oct 18, 2013 at 04:37:05PM +0200, Daniel Vetter wrote: > Really simple, and we don't even have working frame numbers. > = > v2: Actually enable it ... > = > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i= 915_debugfs.c > index e3f0980..3f4fd7c 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inod= e, struct file *file) > return single_open(file, display_crc_ctl_show, dev); > } > = > +static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source, > + uint32_t *val) > +{ > + switch (source) { > + case INTEL_PIPE_CRC_SOURCE_PIPE: > + *val =3D PIPE_CRC_ENABLE; On gen3+ the border is always included in the crc. Maybe we should always include it on gen2 as well? > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, > enum intel_pipe_crc_source source, > uint32_t *val) > @@ -2039,7 +2053,7 @@ static int pipe_crc_set_source(struct drm_device *d= ev, enum pipe pipe, > u32 val; > int ret; > = > - if (!(INTEL_INFO(dev)->gen >=3D 3 && !IS_VALLEYVIEW(dev))) > + if (IS_VALLEYVIEW(dev)) > return -ENODEV; > = > if (pipe_crc->source =3D=3D source) > @@ -2049,7 +2063,9 @@ static int pipe_crc_set_source(struct drm_device *d= ev, enum pipe pipe, > if (pipe_crc->source && source) > return -EINVAL; > = > - if (INTEL_INFO(dev)->gen < 5) > + if (IS_GEN2(dev)) > + ret =3D i8xx_pipe_crc_ctl_reg(source, &val); > + else if (INTEL_INFO(dev)->gen < 5) > ret =3D i9xx_pipe_crc_ctl_reg(dev, source, &val); > else if (IS_GEN5(dev) || IS_GEN6(dev)) > ret =3D ilk_pipe_crc_ctl_reg(source, &val); > -- = > 1.8.4.rc3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC