From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/4] drm/i915: Compute dsi_clk from pixel clock Date: Mon, 21 Oct 2013 16:28:38 +0300 Message-ID: <20131021132838.GY13047@intel.com> References: <1382358067-5578-1-git-send-email-shobhit.kumar@intel.com> <1382358067-5578-4-git-send-email-shobhit.kumar@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 650E5E668D for ; Mon, 21 Oct 2013 06:29:02 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1382358067-5578-4-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Shobhit Kumar Cc: jani.nikula@intel.com, vijayakumar.balakrishnan@intel.com, intel-gfx , yogesh.mohan.marimuthu@intel.com List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 21, 2013 at 05:51:06PM +0530, Shobhit Kumar wrote: > Minor modification to m_n_p calculations as well > = > Signed-off-by: Shobhit Kumar > --- > drivers/gpu/drm/i915/intel_dsi_pll.c | 75 ++++++++++++++++++++++++++++= ------ > 1 file changed, 63 insertions(+), 12 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/= intel_dsi_pll.c > index 44279b2..bf12335 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -50,6 +50,8 @@ static const u32 lfsr_converts[] =3D { > 71, 35 /* 91 - 92 */ > }; > = > +#ifdef DSI_CLK_FROM_RR > + > static u32 dsi_rr_formula(const struct drm_display_mode *mode, > int pixel_format, int video_mode_format, > int lane_count, bool eotp) > @@ -129,6 +131,40 @@ static u32 dsi_rr_formula(const struct drm_display_m= ode *mode, > return dsi_clk; > } > = > +#else > + > +/* Get DSI clock from pixel clock */ > +static u32 dsi_clk_from_pclk(const struct drm_display_mode *mode, > + int pixel_format, int lane_count) > +{ > + u32 dsi_bit_clock_hz, dsi_clk; > + u32 bpp; > + > + switch (pixel_format) { > + default: > + case VID_MODE_FORMAT_RGB888: > + case VID_MODE_FORMAT_RGB666_LOOSE: > + bpp =3D 24; > + break; > + case VID_MODE_FORMAT_RGB666: > + bpp =3D 18; > + break; > + case VID_MODE_FORMAT_RGB565: > + bpp =3D 16; > + break; > + } > + > + /* DSI data rate =3D pixel clock * bits per pixel / lane count > + pixel clock is converted from KHz to Hz */ > + dsi_bit_clock_hz =3D (((mode->clock * 1000) * bpp) / lane_count); > + > + /* DSI clock rate */ > + dsi_clk =3D dsi_bit_clock_hz / (1000 * 1000); > + return dsi_clk; And why is this better than the rr_formula thing that tries to account for the packetization overhead? Also I don't understand why you go from kHz to Hz and then to MHz. I'd just do something like: return DIV_ROUND_CLOSEST(mode->clock * bpp, lane_count); and then change the rest of the code to work in kHz as well. > +} > + > +#endif > + > #ifdef MNP_FROM_TABLE > = > struct dsi_clock_table { > @@ -208,29 +244,42 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp= *dsi_mnp) > ref_clk =3D 25000; > target_dsi_clk =3D dsi_clk * 1000; > error =3D 0xFFFFFFFF; > + tmp_error =3D 0xFFFFFFFF; > calc_m =3D 0; > calc_p =3D 0; > = > for (m =3D 62; m <=3D 92; m++) { > for (p =3D 2; p <=3D 6; p++) { > - > + /* Find the optimal m and p divisors > + with minimal error +/- the required clock */ > calc_dsi_clk =3D (m * ref_clk) / p; > - if (calc_dsi_clk >=3D target_dsi_clk) { > + if (calc_dsi_clk =3D=3D target_dsi_clk) { > + calc_m =3D m; > + calc_p =3D p; > + error =3D 0; > + break; > + } else if (calc_dsi_clk > target_dsi_clk) > tmp_error =3D calc_dsi_clk - target_dsi_clk; > - if (tmp_error < error) { > - error =3D tmp_error; > - calc_m =3D m; > - calc_p =3D p; > - } > + else > + tmp_error =3D target_dsi_clk - calc_dsi_clk; > + > + if (tmp_error < error) { > + error =3D tmp_error; > + calc_m =3D m; > + calc_p =3D p; > } > } > + > + if (error =3D=3D 0) > + break; > } > = > m_seed =3D lfsr_converts[calc_m - 62]; > n =3D 1; > + > dsi_mnp->dsi_pll_ctrl =3D 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); > dsi_mnp->dsi_pll_div =3D (n - 1) << DSI_PLL_N1_DIV_SHIFT | > - m_seed << DSI_PLL_M1_DIV_SHIFT; > + m_seed << DSI_PLL_M1_DIV_SHIFT; > = > return 0; > } > @@ -249,11 +298,13 @@ static void vlv_configure_dsi_pll(struct intel_enco= der *encoder) > struct intel_dsi *intel_dsi =3D enc_to_intel_dsi(&encoder->base); > int ret; > struct dsi_mnp dsi_mnp; > - u32 dsi_clk; > + u32 dsi_clk =3D 0; > = > - dsi_clk =3D dsi_rr_formula(mode, intel_dsi->pixel_format, > - intel_dsi->video_mode_format, > - intel_dsi->lane_count, !intel_dsi->eot_disable); > + if (intel_dsi->dsi_clock_freq) > + dsi_clk =3D intel_dsi->dsi_clock_freq; > + else > + dsi_clk =3D dsi_clk_from_pclk(mode, intel_dsi->pixel_format, > + intel_dsi->lane_count); > = > ret =3D dsi_calc_mnp(dsi_clk, &dsi_mnp); > if (ret) { > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC