From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv Date: Mon, 21 Oct 2013 17:15:40 +0200 Message-ID: <20131021151540.GH4830@phenom.ffwll.local> References: <1381956961-16875-1-git-send-email-daniel.vetter@ffwll.ch> <1381956961-16875-13-git-send-email-daniel.vetter@ffwll.ch> <20131021105003.GU13047@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f169.google.com (mail-ea0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 72E89E6EC6 for ; Mon, 21 Oct 2013 08:15:19 -0700 (PDT) Received: by mail-ea0-f169.google.com with SMTP id k11so3585950eaj.14 for ; Mon, 21 Oct 2013 08:15:18 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20131021105003.GU13047@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 21, 2013 at 01:50:03PM +0300, Ville Syrj=E4l=E4 wrote: > On Wed, Oct 16, 2013 at 10:55:57PM +0200, Daniel Vetter wrote: > > The PIPE_B #define was missing the display mmio offset. Use the > > _PIPE_INC macro instead, it's simpler. > > = > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index ad8fe21..4e0f0b7 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1887,14 +1887,13 @@ > > #define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset = + 0x60080) > > = > > /* Pipe B CRC regs */ > > -#define _PIPE_CRC_CTL_B 0x61050 > > #define _PIPE_CRC_RES_1_B_IVB 0x61064 > > #define _PIPE_CRC_RES_2_B_IVB 0x61068 > > #define _PIPE_CRC_RES_3_B_IVB 0x6106c > > #define _PIPE_CRC_RES_4_B_IVB 0x61070 > > #define _PIPE_CRC_RES_5_B_IVB 0x61074 > = > Maybe use _PIPE_INC() for these IVB regs as well. They're the only CRC > regs left using _PIPE(), so they feel a bit out of place. The _PIPE_INC stuff is essentially just a "throw stuff at the wall and see whether it sticks" test. The idea is that with the doc rework registers for new platforms are already tightly grouped, so the base+increment is easier to review. If people like it we could do a mass conversion (and decently cut down the size of i915_reg.h). That would also help to make the odd cases like vlv+1 stick out more. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch