From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Wire up gen2 CRC support Date: Mon, 21 Oct 2013 18:35:33 +0200 Message-ID: <20131021163533.GJ4830@phenom.ffwll.local> References: <20131021151733.GI4830@phenom.ffwll.local> <1382369198-9773-1-git-send-email-daniel.vetter@ffwll.ch> <20131021161624.GZ13047@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f48.google.com (mail-ee0-f48.google.com [74.125.83.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 759BBE6A16 for ; Mon, 21 Oct 2013 09:35:13 -0700 (PDT) Received: by mail-ee0-f48.google.com with SMTP id e50so2288707eek.21 for ; Mon, 21 Oct 2013 09:35:11 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20131021161624.GZ13047@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 21, 2013 at 07:16:24PM +0300, Ville Syrj=E4l=E4 wrote: > On Mon, Oct 21, 2013 at 05:26:38PM +0200, Daniel Vetter wrote: > > Really simple, and we don't even have working frame numbers. > > = > > v2: Actually enable it ... > > = > > v3: Review from Ville: > > - Unconditionally enable the border in the CRC checksum for > > consistency with gen3+. > > - Handle the "none" source to be able to disable the CRC machinery > > again. > > = > > Cc: Ville Syrj=E4l=E4 > > Signed-off-by: Daniel Vetter > = > Reviewed-by: Ville Syrj=E4l=E4 Thanks for your review, I've merged all the patches to dinq. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch