From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Date: Sun, 27 Oct 2013 13:39:59 +0100 Message-ID: <20131027123959.GB18189@phenom.ffwll.local> References: <1381916088-23330-1-git-send-email-jani.nikula@intel.com> <1381916088-23330-2-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by gabe.freedesktop.org (Postfix) with ESMTP id E65C6E5F99 for ; Sun, 27 Oct 2013 05:39:32 -0700 (PDT) Received: by mail-ee0-f41.google.com with SMTP id d49so2930772eek.14 for ; Sun, 27 Oct 2013 05:39:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: David =?iso-8859-1?Q?H=E4rdeman?= Cc: Jani Nikula , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Oct 24, 2013 at 11:59:35AM +0200, David H=E4rdeman wrote: > It should also be noted that manually hard-coding the pixel clock > value to an obviously incorrect value will also cause the Pioneer > receiver to do the right thing (I assume it will ignore the > incorrect value and calculate it on the fly) - that would point > towards some kind of bug / hardware incompatibility in the Pioneer > receiver. But I agree that the receiver *does* work with other > hardware that I've tried. > = > Attempts to contact Pioneer have been fruitless so far. Maybe Intel > would have better luck there... The hw has shipped, so usually that means you're out of luck. Maybe we simply needs to start adding eld quirks to EDIDs ... -Daniel > = > On 2013-10-24 11:07, Jasper Smet wrote: > >Although i know it also happens in windows, the one particular thing i > >am 'fiddling' with is that when i try the receiver with an nvidia or > >amd apu (ion, e-450 trough hdmi) with my pioneer receiver audio works > >fine with 44100hz at the 1080p@50/60 modes. Only with intel i need to > >force upstreaming to 48000hz. > > > >So are we really sure this is a bug with the receiver or still > >something wrong with the driver / pixel clock issue? > > > >Is there anything else we i do to help ? > > > >On Wed, Oct 16, 2013 at 11:34 AM, Jani Nikula > >wrote: > > > >>The HDMI audio expects HDMI pixel clock to be set in the audio > >>configuration. We've currently just set 0, using 25.2 / 1.001 kHz > >>frequency, which fails with some modes. > >> > >>v2: Now with a commit message. > >> > >>Reference: > >> > >http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g= @mail.gmail.com > >>[1] > >>Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu > >>Reported-by: David H=E4rdeman > >>Reported-by: Jasper Smet > >>Tested-by: Jasper Smet > >>Signed-off-by: Jani Nikula > >>--- > >>=A0drivers/gpu/drm/i915/i915_reg.h =A0 =A0 =A0| =A0 12 ++++++++- > >>=A0drivers/gpu/drm/i915/intel_display.c | =A0 48 > >>+++++++++++++++++++++++++++++++--- > >>=A02 files changed, 55 insertions(+), 5 deletions(-) > >> > >>diff --git a/drivers/gpu/drm/i915/i915_reg.h > >>b/drivers/gpu/drm/i915/i915_reg.h > >>index 13153c3..3266819 100644 > >>--- a/drivers/gpu/drm/i915/i915_reg.h > >>+++ b/drivers/gpu/drm/i915/i915_reg.h > >>@@ -4875,7 +4875,17 @@ > >>=A0#define =A0 AUD_CONFIG_LOWER_N_SHIFT =A0 =A0 =A0 =A0 =A0 =A0 4 > >>=A0#define =A0 AUD_CONFIG_LOWER_N_VALUE =A0 =A0 =A0 =A0 =A0 =A0 (0xfff = << > >>4) > >>=A0#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT =A0 =A016 > >>-#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI =A0 =A0 =A0 =A0 =A0(0xf << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK =A0 =A0 (0xf << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 =A0 =A0(0 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 =A0 =A0(1 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 =A0 =A0(2 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 =A0 =A0(3 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 =A0 =A0(4 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 =A0 =A0(5 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 =A0 =A0(6 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 =A0 =A0(7 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 =A0 (8 << 16) > >>+#define =A0 AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 =A0 (9 << 16) > >>=A0#define =A0 AUD_CONFIG_DISABLE_NCTS =A0 =A0 =A0 =A0 =A0 =A0 =A0(1 <<= 3) > >> > >>=A0/* HSW Audio */ > >>diff --git a/drivers/gpu/drm/i915/intel_display.c > >>b/drivers/gpu/drm/i915/intel_display.c > >>index 55740f2..a097f84 100644 > >>--- a/drivers/gpu/drm/i915/intel_display.c > >>+++ b/drivers/gpu/drm/i915/intel_display.c > >>@@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct > >>drm_crtc *crtc, > >>=A0 =A0 =A0 =A0 return 0; > >>=A0} > >> > >>+static struct { > >>+ =A0 =A0 =A0 int clock; > >>+ =A0 =A0 =A0 u32 config; > >>+} hdmi_audio_clock[] =3D { > >>+ =A0 =A0 =A0 { DIV_ROUND_UP(25200 * 1000, 1001), > >>AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, > >>+ =A0 =A0 =A0 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default > >>per bspec */ > >>+ =A0 =A0 =A0 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, > >>+ =A0 =A0 =A0 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 > >>}, > >>+ =A0 =A0 =A0 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, > >>+ =A0 =A0 =A0 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 > >>}, > >>+ =A0 =A0 =A0 { DIV_ROUND_UP(74250 * 1000, 1001), > >>AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, > >>+ =A0 =A0 =A0 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, > >>+ =A0 =A0 =A0 { DIV_ROUND_UP(148500 * 1000, 1001), > >>AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, > >>+ =A0 =A0 =A0 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, > >>+}; > >>+ > >>+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ > >>+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode > >>*mode) > >>+{ > >>+ =A0 =A0 =A0 int i; > >>+ > >>+ =A0 =A0 =A0 for (i =3D 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mode->clock =3D=3D > >>hdmi_audio_clock[i].clock) > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > >>+ =A0 =A0 =A0 } > >>+ > >>+ =A0 =A0 =A0 if (i =3D=3D ARRAY_SIZE(hdmi_audio_clock)) { > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 DRM_DEBUG_KMS("HDMI audio pixel clock > >>setting for %d not found, falling back to defaultsn", mode->clock); > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 i =3D 1; > >>+ =A0 =A0 =A0 } > >>+ > >>+ =A0 =A0 =A0 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d > >>(0x%08x)n", > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 hdmi_audio_clock[i].clock, > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 hdmi_audio_clock[i].config); > >>+ > >>+ =A0 =A0 =A0 return hdmi_audio_clock[i].config; > >>+} > >>+ > >>=A0static bool intel_eld_uptodate(struct drm_connector *connector, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0int reg_= eldv, > >>uint32_t bits_eldv, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0int reg_= elda, > >>uint32_t bits_elda, > >>@@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct > >>drm_connector *connector, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DRM_DEBUG_DRIVER("ELD: DisplayPort > >>detectedn"); > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 eld[5] |=3D (1 << 2); =A0 =A0 /* Conn_T= ype, 0x1 > >>=3D DisplayPort */ > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, > >>AUD_CONFIG_N_VALUE_INDEX); /* 0x1 =3D DP */ > >>- =A0 =A0 =A0 } else > >>- =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, 0); > >>+ =A0 =A0 =A0 } else { > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, > >>audio_config_hdmi_pixel_clock(mode)); > >>+ =A0 =A0 =A0 } > >> > >>=A0 =A0 =A0 =A0 if (intel_eld_uptodate(connector, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0aud_cntr= l_st2, eldv, > >>@@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct > >>drm_connector *connector, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DRM_DEBUG_DRIVER("ELD: DisplayPort > >>detectedn"); > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 eld[5] |=3D (1 << 2); =A0 =A0 /* Conn_T= ype, 0x1 > >>=3D DisplayPort */ > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, > >>AUD_CONFIG_N_VALUE_INDEX); /* 0x1 =3D DP */ > >>- =A0 =A0 =A0 } else > >>- =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, 0); > >>+ =A0 =A0 =A0 } else { > >>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(aud_config, > >>audio_config_hdmi_pixel_clock(mode)); > >>+ =A0 =A0 =A0 } > >> > >>=A0 =A0 =A0 =A0 if (intel_eld_uptodate(connector, > >>=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0aud_cntr= l_st2, eldv, > >>-- > >>1.7.9.5 > > > >-- > >Met Vriendelijke Groeten > > > >Jasper Smet > >Developer > > > >Twitter: josbeir > >E-mail: josbeir@gmail.com > > Mobile: 0486/41.75.45 > > > >Links: > >------ > >[1] > >http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g= @mail.gmail.com > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch