From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Fix the PPT fdi lane bifurcate state handling on ivb Date: Tue, 29 Oct 2013 13:52:34 +0100 Message-ID: <20131029125234.GU18189@phenom.ffwll.local> References: <1383044648-15603-1-git-send-email-daniel.vetter@ffwll.ch> <20131029124610.GU13047@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <20131029124610.GU13047@intel.com> Sender: stable-owner@vger.kernel.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Oct 29, 2013 at 02:46:10PM +0200, Ville Syrj=E4l=E4 wrote: > On Tue, Oct 29, 2013 at 12:04:08PM +0100, Daniel Vetter wrote: > > Originally I've thought that this is leftover hw state dirt from th= e > > BIOS. But after way too much helpless flailing around on my part I'= ve > > noticed that the actual bug is when we change the state of an alrea= dy > > active pipe. > >=20 > > For example when we change the fdi lines from 2 to 3 without switch= ing > > off outputs in-between we'll never see the crucial on->off transiti= on > > in the ->modeset_global_resources hook the current logic relies on. > >=20 > > Patch version 2 got this right by instead also checking whether the > > pipe is indeed active. But that in turn broke things when pipes hav= e > > been turned off through dpms since the bifurcate enabling is done i= n > > the ->crtc_mode_set callback. > >=20 > > To address this issues discussed with Ville in the patch review mov= e > > the setting of the bifurcate bit into the ->crtc_enable hook. That = way > > we won't wreak havoc with this state when userspace puts all other > > outputs into dpms off state. This also moves us forward with our > > overall goal to unify the modeset and dpms on paths (which we need = to > > have to allow runtime pm in the dpms off state). > >=20 > > Unfortunately this requires us to move the bifurcate helpers around= a > > bit. > >=20 > > Also update the commit message, I've misanalyzed the bug rather bad= ly. > >=20 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D70507 > > Tested-by: Jan-Michael Brummer > > Cc: stable@vger.kernel.org > > Cc: Ville Syrj=E4l=E4 > > Signed-off-by: Daniel Vetter >=20 > Reviewed-by: Ville Syrj=E4l=E4 >=20 > And since it now calls cpt_enable_fdi_bc_bifurcation() only when=20 > has_pch_encoder=3D=3Dtrue it should also fix the following scenario: >=20 > 1. setcrtc pipe B -> PCH w/ fdi_lanes>2 > 2. setcrtc pipe C -> eDP >=20 > Previously the pipe C .mode_set() whould have called > cpt_enable_fdi_bc_bifurcation() unconditionally, which > would have killed pipe B. Geez, did that take a while for me to sink in. Somehow I've thought I'v= e fixed this a long time ago so that cpu edp on pipe C allows us to fully use the fdi links on pipes A/B. But reading through the code again I've only updated the logic in the compute_config stage, not here. Thanks for your review, patch merged to -fixes. -Daniel >=20 > > --- > > drivers/gpu/drm/i915/intel_display.c | 95 ++++++++++++++++++------= ------------ > > 1 file changed, 48 insertions(+), 47 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm= /i915/intel_display.c > > index 8c3bf8a89cb7..509762c85d2e 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2421,9 +2421,10 @@ static void intel_fdi_normal_train(struct dr= m_crtc *crtc) > > FDI_FE_ERRC_ENABLE); > > } > > =20 > > -static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) > > +static bool pipe_has_enabled_pch(struct intel_crtc *crtc) > > { > > - return intel_crtc->base.enabled && intel_crtc->config.has_pch_enc= oder; > > + return crtc->base.enabled && crtc->active && > > + crtc->config.has_pch_encoder; > > } > > =20 > > static void ivb_modeset_global_resources(struct drm_device *dev) > > @@ -3074,6 +3075,48 @@ static void ironlake_pch_transcoder_set_timi= ngs(struct intel_crtc *crtc, > > I915_READ(VSYNCSHIFT(cpu_transcoder))); > > } > > =20 > > +static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) > > +{ > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + uint32_t temp; > > + > > + temp =3D I915_READ(SOUTH_CHICKEN1); > > + if (temp & FDI_BC_BIFURCATION_SELECT) > > + return; > > + > > + WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); > > + WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); > > + > > + temp |=3D FDI_BC_BIFURCATION_SELECT; > > + DRM_DEBUG_KMS("enabling fdi C rx\n"); > > + I915_WRITE(SOUTH_CHICKEN1, temp); > > + POSTING_READ(SOUTH_CHICKEN1); > > +} > > + > > +static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc = *intel_crtc) > > +{ > > + struct drm_device *dev =3D intel_crtc->base.dev; > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + > > + switch (intel_crtc->pipe) { > > + case PIPE_A: > > + break; > > + case PIPE_B: > > + if (intel_crtc->config.fdi_lanes > 2) > > + WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); > > + else > > + cpt_enable_fdi_bc_bifurcation(dev); > > + > > + break; > > + case PIPE_C: > > + cpt_enable_fdi_bc_bifurcation(dev); > > + > > + break; > > + default: > > + BUG(); > > + } > > +} > > + > > /* > > * Enable PCH resources required for PCH ports: > > * - PCH PLLs > > @@ -3092,6 +3135,9 @@ static void ironlake_pch_enable(struct drm_cr= tc *crtc) > > =20 > > assert_pch_transcoder_disabled(dev_priv, pipe); > > =20 > > + if (IS_IVYBRIDGE(dev)) > > + ivybridge_update_fdi_bc_bifurcation(intel_crtc); > > + > > /* Write the TU size bits before fdi link training, so that error > > * detection works. */ > > I915_WRITE(FDI_RX_TUSIZE1(pipe), > > @@ -5849,48 +5895,6 @@ static bool ironlake_compute_clocks(struct d= rm_crtc *crtc, > > return true; > > } > > =20 > > -static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) > > -{ > > - struct drm_i915_private *dev_priv =3D dev->dev_private; > > - uint32_t temp; > > - > > - temp =3D I915_READ(SOUTH_CHICKEN1); > > - if (temp & FDI_BC_BIFURCATION_SELECT) > > - return; > > - > > - WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); > > - WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); > > - > > - temp |=3D FDI_BC_BIFURCATION_SELECT; > > - DRM_DEBUG_KMS("enabling fdi C rx\n"); > > - I915_WRITE(SOUTH_CHICKEN1, temp); > > - POSTING_READ(SOUTH_CHICKEN1); > > -} > > - > > -static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc = *intel_crtc) > > -{ > > - struct drm_device *dev =3D intel_crtc->base.dev; > > - struct drm_i915_private *dev_priv =3D dev->dev_private; > > - > > - switch (intel_crtc->pipe) { > > - case PIPE_A: > > - break; > > - case PIPE_B: > > - if (intel_crtc->config.fdi_lanes > 2) > > - WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); > > - else > > - cpt_enable_fdi_bc_bifurcation(dev); > > - > > - break; > > - case PIPE_C: > > - cpt_enable_fdi_bc_bifurcation(dev); > > - > > - break; > > - default: > > - BUG(); > > - } > > -} > > - > > int ironlake_get_lanes_required(int target_clock, int link_bw, int= bpp) > > { > > /* > > @@ -6079,9 +6083,6 @@ static int ironlake_crtc_mode_set(struct drm_= crtc *crtc, > > &intel_crtc->config.fdi_m_n); > > } > > =20 > > - if (IS_IVYBRIDGE(dev)) > > - ivybridge_update_fdi_bc_bifurcation(intel_crtc); > > - > > ironlake_set_pipeconf(crtc); > > =20 > > /* Set up the display plane register */ > > --=20 > > 1.8.4.rc3 >=20 > --=20 > Ville Syrj=E4l=E4 > Intel OTC --=20 Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch