From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 4/8] drm/i915: s/HAS_POWER_WELL/IS_HASWELL/ in intel_display_capture_error_state Date: Fri, 1 Nov 2013 20:41:40 +0100 Message-ID: <20131101194140.GV4167@phenom.ffwll.local> References: <1383326394-3933-1-git-send-email-imre.deak@intel.com> <1383326394-3933-5-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f175.google.com (mail-ea0-f175.google.com [209.85.215.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F022F077C for ; Fri, 1 Nov 2013 12:41:13 -0700 (PDT) Received: by mail-ea0-f175.google.com with SMTP id l15so1861465eak.34 for ; Fri, 01 Nov 2013 12:41:12 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1383326394-3933-5-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Nov 01, 2013 at 07:19:50PM +0200, Imre Deak wrote: > Some upcoming platforms with power wells don't have this register, so > check for Haswell instead. > > Signed-off-by: Imre Deak The point of HAS_POWER_WELL was to make bdw work (for which we now have approval apparently). Depending upon how this all shapes out it's probably better to stall this series for a little bit until the bdw stuff has landed. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 8f40ae3..929ecce 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11101,7 +11101,7 @@ intel_display_capture_error_state(struct drm_device *dev) > if (error == NULL) > return NULL; > > - if (HAS_POWER_WELL(dev)) > + if (IS_HASWELL(dev)) > error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); > > for_each_pipe(i) { > @@ -11171,7 +11171,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, > return; > > err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); > - if (HAS_POWER_WELL(dev)) > + if (IS_HASWELL(dev)) > err_printf(m, "PWR_WELL_CTL2: %08x\n", > error->power_well_driver); > for_each_pipe(i) { > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch