From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority Date: Sun, 3 Nov 2013 13:07:58 +0200 Message-ID: <20131103110758.GL13047@intel.com> References: <1383451680-11173-1-git-send-email-benjamin.widawsky@intel.com> <1383451680-11173-43-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E8D8EE8A6 for ; Sun, 3 Nov 2013 03:08:02 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383451680-11173-43-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Sat, Nov 02, 2013 at 09:07:40PM -0700, Ben Widawsky wrote: > GEN8 also needs this workaround. Not according to the w/a database. But the register description is the same for both HSW and BDW. Also for HSW, the w/a doesn't actually say whether we should set or clear the bit. the default is listed to be 0, so I guess we should set it, but then it's unclear why BDW wouldn't need the w/a. Once again a very poorly docuemnted w/a :( > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index caf31b7..68dc363 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5192,6 +5192,9 @@ static void gen8_init_clock_gating(struct drm_devic= e *dev) > I915_WRITE(WM3_LP_ILK, 0); > I915_WRITE(WM2_LP_ILK, 0); > I915_WRITE(WM1_LP_ILK, 0); > + > + /* WaSwitchSolVfFArbitrationPriority */ > + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > } > = > static void haswell_init_clock_gating(struct drm_device *dev) > -- = > 1.8.4.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC