From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH] drm/i915: flush cursors harder Date: Mon, 4 Nov 2013 18:02:24 +0200 Message-ID: <20131104160224.GT13047@intel.com> References: <1383549225-16841-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1383549225-16841-1-git-send-email-daniel.vetter@ffwll.ch> Sender: stable-owner@vger.kernel.org To: Daniel Vetter Cc: Intel Graphics Development , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Nov 04, 2013 at 08:13:45AM +0100, Daniel Vetter wrote: > Apparently they need the same treatment as primary planes. This fixes > modesetting failures because of stuck cursors (!) on Thomas' i830M > machine. What treatment? Primary planes don't need any extra posting reads AFAIK= =2E >=20 > I've figured while at it I'll also roll it out for the ivb 3 pipe > version of this function. I didn't do this for i845/i865 since Bspec > says the update mechanism works differently, and there's some > additional rules about what can be updated in which order. >=20 > Tested-by: Thomas Richter I didn't see an explicit note from Thomas saying that he tested it. > Cc: stable@vger.kernel.org > Cc: Thomas Richter > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i= 915/intel_display.c > index f34252d134b6..04d2699f51b4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7123,7 +7123,9 @@ static void i9xx_update_cursor(struct drm_crtc = *crtc, u32 base) > intel_crtc->cursor_visible =3D visible; > } > /* and commit changes on next vblank */ > + POSTING_READ(CURCNTR(pipe)); > I915_WRITE(CURBASE(pipe), base); > + POSTING_READ(CURBASE(pipe)); > } > =20 > static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) > @@ -7152,7 +7154,9 @@ static void ivb_update_cursor(struct drm_crtc *= crtc, u32 base) > intel_crtc->cursor_visible =3D visible; > } > /* and commit changes on next vblank */ > + POSTING_READ(CURCNTR_IVB(pipe)); > I915_WRITE(CURBASE_IVB(pipe), base); > + POSTING_READ(CURBASE_IVB(pipe)); > } > =20 > /* If no-part of the cursor is visible on the framebuffer, then the = GPU may hang... */ > --=20 > 1.8.4.rc3 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC