From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: flush cursors harder Date: Mon, 4 Nov 2013 17:34:41 +0100 Message-ID: <20131104163441.GM4167@phenom.ffwll.local> References: <1383549225-16841-1-git-send-email-daniel.vetter@ffwll.ch> <20131104160224.GT13047@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by gabe.freedesktop.org (Postfix) with ESMTP id 77B05FA9A0 for ; Mon, 4 Nov 2013 08:34:14 -0800 (PST) Received: by mail-ee0-f44.google.com with SMTP id d41so1083867eek.31 for ; Mon, 04 Nov 2013 08:34:13 -0800 (PST) Content-Disposition: inline In-Reply-To: <20131104160224.GT13047@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Nov 04, 2013 at 06:02:24PM +0200, Ville Syrj=E4l=E4 wrote: > On Mon, Nov 04, 2013 at 08:13:45AM +0100, Daniel Vetter wrote: > > Apparently they need the same treatment as primary planes. This fixes > > modesetting failures because of stuck cursors (!) on Thomas' i830M > > machine. > = > What treatment? Primary planes don't need any extra posting reads AFAIK. If you look at flush_primary_plane it's definitely there. So I've copied it over (it's just a real I915_READ, not a posting one). > = > > = > > I've figured while at it I'll also roll it out for the ivb 3 pipe > > version of this function. I didn't do this for i845/i865 since Bspec > > says the update mechanism works differently, and there's some > > additional rules about what can be updated in which order. > > = > > Tested-by: Thomas Richter > = > I didn't see an explicit note from Thomas saying that he tested it. It's burried somewhere in the thread, but he said that with the 2 earlier dvo patches + this one here the lvds-only use-case now works well. Before that he had issues with the display just showing a cursor and the kernel complaining about the cursor being stuck in the enabled position when trying to re-enable it. -Daniel > = > > Cc: stable@vger.kernel.org > > Cc: Thomas Richter > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index f34252d134b6..04d2699f51b4 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -7123,7 +7123,9 @@ static void i9xx_update_cursor(struct drm_crtc *c= rtc, u32 base) > > intel_crtc->cursor_visible =3D visible; > > } > > /* and commit changes on next vblank */ > > + POSTING_READ(CURCNTR(pipe)); > > I915_WRITE(CURBASE(pipe), base); > > + POSTING_READ(CURBASE(pipe)); > > } > > = > > static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) > > @@ -7152,7 +7154,9 @@ static void ivb_update_cursor(struct drm_crtc *cr= tc, u32 base) > > intel_crtc->cursor_visible =3D visible; > > } > > /* and commit changes on next vblank */ > > + POSTING_READ(CURCNTR_IVB(pipe)); > > I915_WRITE(CURBASE_IVB(pipe), base); > > + POSTING_READ(CURBASE_IVB(pipe)); > > } > > = > > /* If no-part of the cursor is visible on the framebuffer, then the GP= U may hang... */ > > -- = > > 1.8.4.rc3 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch