From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Date: Tue, 5 Nov 2013 00:49:57 +0200 Message-ID: <20131104224957.GD13047@intel.com> References: <1383594766-6042-1-git-send-email-jbarnes@virtuousgeek.org> <1383594766-6042-2-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 18CDE1127A1 for ; Mon, 4 Nov 2013 14:50:00 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383594766-6042-2-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Nov 04, 2013 at 11:52:45AM -0800, Jesse Barnes wrote: > We don't want it delayed with the RPS work. > = > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++------------- > 1 file changed, 18 insertions(+), 13 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index a0c907f..2e7072e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4064,19 +4064,6 @@ static void valleyview_enable_rps(struct drm_devic= e *dev) > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > = > val =3D vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > - switch ((val >> 6) & 3) { > - case 0: > - case 1: > - dev_priv->mem_freq =3D 800; > - break; > - case 2: > - dev_priv->mem_freq =3D 1066; > - break; > - case 3: > - dev_priv->mem_freq =3D 1333; > - break; > - } > - DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > = > DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); > DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); > @@ -5325,6 +5312,24 @@ static void ivybridge_init_clock_gating(struct drm= _device *dev) > static void valleyview_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > + u32 val; > + > + mutex_lock(&dev_priv->rps.hw_lock); > + val =3D vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > + mutex_unlock(&dev_priv->rps.hw_lock); > + switch ((val >> 6) & 3) { > + case 0: > + case 1: > + dev_priv->mem_freq =3D 800; > + break; > + case 2: > + dev_priv->mem_freq =3D 1066; > + break; > + case 3: > + dev_priv->mem_freq =3D 1333; > + break; > + } This doesn't actually match the punit HAS I have. What I see is 0=3D800, 1=3D1066, 2=3D1333, 3=3Dinvalid. But using the DDR rate to determine the CCK clock isn't the best idea I think. It seems there's an option of running CCK at 800MHz even for the DDR 1066 case. So I think we should just use CCK_FUSE_REG to figure it out, just like gmbus_set_freq() already does. > + DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > = > I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > = > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC