From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 22/62] drm/i915/bdw: Implement Full Force Miss disables Date: Tue, 5 Nov 2013 17:17:26 +0100 Message-ID: <20131105161726.GC1775@phenom.ffwll.local> References: <1383451680-11173-1-git-send-email-benjamin.widawsky@intel.com> <1383451680-11173-23-git-send-email-benjamin.widawsky@intel.com> <1383666081.7273.11.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f180.google.com (mail-ea0-f180.google.com [209.85.215.180]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C382FB691 for ; Tue, 5 Nov 2013 08:16:58 -0800 (PST) Received: by mail-ea0-f180.google.com with SMTP id b11so348260eae.25 for ; Tue, 05 Nov 2013 08:16:57 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383666081.7273.11.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: Intel GFX , Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Tue, Nov 05, 2013 at 05:41:21PM +0200, Imre Deak wrote: > On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote: > > Implements WaVSRefCountFullforceMissDisable > > Implements WaDSRefCountFullforceMissDisable > > = > > v2: Rebased on the HSW patch (which fixed the bug from v1) > > commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7 > > Author: Ben Widawsky > > Date: Sat Jan 26 11:52:00 2013 -0800 > > = > > drm/i915: Implement WaVSRefCountFullforceMissDisable > > = > > Cc: Ville Syrj=E4l=E4 > > Reviewed-by: Ville Syrj=E4l=E4 > > Signed-off-by: Ben Widawsky > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > > 2 files changed, 5 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 9929750..68b877d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -990,6 +990,7 @@ > > = > > #define GEN7_FF_THREAD_MODE 0x20a0 > > #define GEN7_FF_SCHED_MASK 0x0077070 > > +#define GEN7_FF_DS_REF_CNT_FFME (1 << 19) > > #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) > > #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) > > #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index abc51ea..81ec2c3 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5147,6 +5147,10 @@ static void gen7_setup_fixed_func_scheduler(stru= ct drm_i915_private *dev_priv) > > if (IS_HASWELL(dev_priv->dev)) > > reg &=3D ~GEN7_FF_VS_REF_CNT_FFME; > > = > > + /* WaVSRefCountFullforceMissDisable|WaDSRefCountFullforceMissDisable = */ > > + if (IS_GEN8(dev_priv->dev)) > > + reg &=3D ~(GEN7_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME); > > + > > I915_WRITE(GEN7_FF_THREAD_MODE, reg); > > } > = > gen7_setup_fixed_func_scheduler() isn't called for GEN8. I've just looked at the history of the quilt tree and it's been like that ever since I've merged the patch apparently. Probably mis-wiggled while applying ... Ben, should I just move this to the gen8 clock gating? -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch