From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 1/2] drm/i915/vlv: split CCK and DDR freq
 usage
Date: Tue, 5 Nov 2013 19:31:49 +0100
Message-ID: <20131105183149.GD1775@phenom.ffwll.local>
References: <1383610020-2202-1-git-send-email-jbarnes@virtuousgeek.org>
	<20131105112449.GE13047@intel.com>
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To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
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On Tue, Nov 05, 2013 at 01:24:49PM +0200, Ville Syrj=E4l=E4 wrote:
> On Mon, Nov 04, 2013 at 04:06:59PM -0800, Jesse Barnes wrote:
> > It's possible that the CCK clock could run at a different rate than the
> > DDR clock, so use the same method to get CCK as the GMBUS code does when
> > calculating the new CDclk divider in the VLV display code.
> > =

> > Reported-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> =

> For the series:
> Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

Both series merged, thanks for patches and review.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch