* [PATCH 0/4] drm/i915: VLV graphics clock improvements
@ 2013-11-05 20:42 ville.syrjala
2013-11-05 20:42 ` [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() ville.syrjala
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: ville.syrjala @ 2013-11-05 20:42 UTC (permalink / raw)
To: intel-gfx
After I started looking into how various things are clocked in VLV, I
noticed that we miscalculate the graphics clock a bit. So I set out to
fix it, and while doing that I figured why not implement the same code
for GPLL bypass mode. Supposedly there aren't any systems that use that
mode currently, but I perhaps in the future...
This was not actually tested on real hardware, but at least the numbers
the new code produces match the spec better than the old code.
Ville Syrjälä (4):
drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode()
drm/i915: Pass dev_priv to vlv_gpu_freq() and vlv_freq_opcode()
drm/i915: Store HPLL frequency in dev_priv on VLV
drm/i915: Add support for VLV GPLL bypass
drivers/gpu/drm/i915/i915_debugfs.c | 17 +++----
drivers/gpu/drm/i915/i915_drv.h | 7 +--
drivers/gpu/drm/i915/i915_sysfs.c | 13 +++--
drivers/gpu/drm/i915/intel_display.c | 7 ++-
drivers/gpu/drm/i915/intel_pm.c | 93 +++++++++++++++++++-----------------
5 files changed, 72 insertions(+), 65 deletions(-)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() 2013-11-05 20:42 [PATCH 0/4] drm/i915: VLV graphics clock improvements ville.syrjala @ 2013-11-05 20:42 ` ville.syrjala 2013-11-06 16:56 ` Jesse Barnes 2013-11-05 20:42 ` [PATCH 2/4] drm/i915: Pass dev_priv to " ville.syrjala ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: ville.syrjala @ 2013-11-05 20:42 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> We're currently miscalculating the VLV graphics clock a little bit. This is caused by rounding the step to integer MHz, which does not match reality. Change the formula to match the GUnit HAS to give more accurate answers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 35 ++++++++++++----------------------- 1 file changed, 12 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a5778e5..865035b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5947,57 +5947,46 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) int vlv_gpu_freq(int ddr_freq, int val) { - int mult, base; + int div; + /* 4 x czclk */ switch (ddr_freq) { case 800: - mult = 20; - base = 120; + div = 10; break; case 1066: - mult = 22; - base = 133; + div = 12; break; case 1333: - mult = 21; - base = 125; + div = 16; break; default: return -1; } - return ((val - 0xbd) * mult) + base; + return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div); } int vlv_freq_opcode(int ddr_freq, int val) { - int mult, base; + int mul; + /* 4 x czclk */ switch (ddr_freq) { case 800: - mult = 20; - base = 120; + mul = 10; break; case 1066: - mult = 22; - base = 133; + mul = 12; break; case 1333: - mult = 21; - base = 125; + mul = 16; break; default: return -1; } - val /= mult; - val -= base / mult; - val += 0xbd; - - if (val > 0xea) - val = 0xea; - - return val; + return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6; } void intel_pm_init(struct drm_device *dev) -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() 2013-11-05 20:42 ` [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() ville.syrjala @ 2013-11-06 16:56 ` Jesse Barnes 0 siblings, 0 replies; 13+ messages in thread From: Jesse Barnes @ 2013-11-06 16:56 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, 5 Nov 2013 22:42:28 +0200 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We're currently miscalculating the VLV graphics clock a little bit. > This is caused by rounding the step to integer MHz, which does not > match reality. Change the formula to match the GUnit HAS to give > more accurate answers. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 35 ++++++++++++----------------------- > 1 file changed, 12 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a5778e5..865035b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5947,57 +5947,46 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > > int vlv_gpu_freq(int ddr_freq, int val) > { > - int mult, base; > + int div; > > + /* 4 x czclk */ > switch (ddr_freq) { > case 800: > - mult = 20; > - base = 120; > + div = 10; > break; > case 1066: > - mult = 22; > - base = 133; > + div = 12; > break; > case 1333: > - mult = 21; > - base = 125; > + div = 16; > break; > default: > return -1; > } > > - return ((val - 0xbd) * mult) + base; > + return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div); > } > > int vlv_freq_opcode(int ddr_freq, int val) > { > - int mult, base; > + int mul; > > + /* 4 x czclk */ > switch (ddr_freq) { > case 800: > - mult = 20; > - base = 120; > + mul = 10; > break; > case 1066: > - mult = 22; > - base = 133; > + mul = 12; > break; > case 1333: > - mult = 21; > - base = 125; > + mul = 16; > break; > default: > return -1; > } > > - val /= mult; > - val -= base / mult; > - val += 0xbd; > - > - if (val > 0xea) > - val = 0xea; > - > - return val; > + return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6; > } > > void intel_pm_init(struct drm_device *dev) Yeah these values look better at 1066 and 1333. No differences at 800 though. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/4] drm/i915: Pass dev_priv to vlv_gpu_freq() and vlv_freq_opcode() 2013-11-05 20:42 [PATCH 0/4] drm/i915: VLV graphics clock improvements ville.syrjala 2013-11-05 20:42 ` [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() ville.syrjala @ 2013-11-05 20:42 ` ville.syrjala 2013-11-05 21:01 ` Jesse Barnes 2013-11-05 20:42 ` [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV ville.syrjala 2013-11-05 20:42 ` [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass ville.syrjala 3 siblings, 1 reply; 13+ messages in thread From: ville.syrjala @ 2013-11-05 20:42 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> We'll be looking at more than just mem_freq from dev_priv, so just pass the whole thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++---------- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_sysfs.c | 13 ++++++------- drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++--------------------- 4 files changed, 31 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7008aac..9770c2f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -974,15 +974,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); seq_printf(m, "max GPU freq: %d MHz\n", - vlv_gpu_freq(dev_priv->mem_freq, val)); + vlv_gpu_freq(dev_priv, val)); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); seq_printf(m, "min GPU freq: %d MHz\n", - vlv_gpu_freq(dev_priv->mem_freq, val)); + vlv_gpu_freq(dev_priv, val)); seq_printf(m, "current GPU freq: %d MHz\n", - vlv_gpu_freq(dev_priv->mem_freq, - (freq_sts >> 8) & 0xff)); + vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); mutex_unlock(&dev_priv->rps.hw_lock); } else { seq_puts(m, "no P-state info available\n"); @@ -2725,8 +2724,7 @@ i915_max_freq_get(void *data, u64 *val) return ret; if (IS_VALLEYVIEW(dev)) - *val = vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.max_delay); + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); else *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; mutex_unlock(&dev_priv->rps.hw_lock); @@ -2756,7 +2754,7 @@ i915_max_freq_set(void *data, u64 val) * Turbo will still be enabled, but won't go above the set value. */ if (IS_VALLEYVIEW(dev)) { - val = vlv_freq_opcode(dev_priv->mem_freq, val); + val = vlv_freq_opcode(dev_priv, val); dev_priv->rps.max_delay = val; gen6_set_rps(dev, val); } else { @@ -2791,8 +2789,7 @@ i915_min_freq_get(void *data, u64 *val) return ret; if (IS_VALLEYVIEW(dev)) - *val = vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.min_delay); + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); else *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; mutex_unlock(&dev_priv->rps.hw_lock); @@ -2822,7 +2819,7 @@ i915_min_freq_set(void *data, u64 val) * Turbo will still be enabled, but won't go below the set value. */ if (IS_VALLEYVIEW(dev)) { - val = vlv_freq_opcode(dev_priv->mem_freq, val); + val = vlv_freq_opcode(dev_priv, val); dev_priv->rps.min_delay = val; valleyview_set_rps(dev, val); } else { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2aa7053..4bae871 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2412,8 +2412,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, enum intel_sbi_destination destination); -int vlv_gpu_freq(int ddr_freq, int val); -int vlv_freq_opcode(int ddr_freq, int val); +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index cef38fd..5e81cf1 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, if (IS_VALLEYVIEW(dev_priv->dev)) { u32 freq; freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); - ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); + ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); } else { ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; } @@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, struct drm_i915_private *dev_priv = dev->dev_private; return snprintf(buf, PAGE_SIZE, "%d\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.rpe_delay)); + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay)); } static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) @@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute mutex_lock(&dev_priv->rps.hw_lock); if (IS_VALLEYVIEW(dev_priv->dev)) - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay); + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); else ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; mutex_unlock(&dev_priv->rps.hw_lock); @@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, mutex_lock(&dev_priv->rps.hw_lock); if (IS_VALLEYVIEW(dev_priv->dev)) { - val = vlv_freq_opcode(dev_priv->mem_freq, val); + val = vlv_freq_opcode(dev_priv, val); hw_max = valleyview_rps_max_freq(dev_priv); hw_min = valleyview_rps_min_freq(dev_priv); @@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute mutex_lock(&dev_priv->rps.hw_lock); if (IS_VALLEYVIEW(dev_priv->dev)) - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay); + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); else ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; mutex_unlock(&dev_priv->rps.hw_lock); @@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, mutex_lock(&dev_priv->rps.hw_lock); if (IS_VALLEYVIEW(dev)) { - val = vlv_freq_opcode(dev_priv->mem_freq, val); + val = vlv_freq_opcode(dev_priv, val); hw_max = valleyview_rps_max_freq(dev_priv); hw_min = valleyview_rps_min_freq(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 865035b..f5bb9b3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3609,9 +3609,9 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv) if (pval != dev_priv->rps.cur_delay) DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), dev_priv->rps.cur_delay, - vlv_gpu_freq(dev_priv->mem_freq, pval), pval); + vlv_gpu_freq(dev_priv, pval), pval); dev_priv->rps.cur_delay = pval; } @@ -3629,10 +3629,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) vlv_update_rps_cur_delay(dev_priv); DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.cur_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), dev_priv->rps.cur_delay, - vlv_gpu_freq(dev_priv->mem_freq, val), val); + vlv_gpu_freq(dev_priv, val), val); if (val == dev_priv->rps.cur_delay) return; @@ -3641,7 +3640,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) dev_priv->rps.cur_delay = val; - trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); + trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); } static void gen6_disable_rps_interrupts(struct drm_device *dev) @@ -4070,32 +4069,27 @@ static void valleyview_enable_rps(struct drm_device *dev) dev_priv->rps.cur_delay = (val >> 8) & 0xff; DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.cur_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), dev_priv->rps.cur_delay); dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); dev_priv->rps.hw_max = dev_priv->rps.max_delay; DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.max_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay), dev_priv->rps.max_delay); dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.rpe_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), dev_priv->rps.rpe_delay); dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.min_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay), dev_priv->rps.min_delay); DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.rpe_delay), + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), dev_priv->rps.rpe_delay); valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); @@ -5945,12 +5939,12 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) return 0; } -int vlv_gpu_freq(int ddr_freq, int val) +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) { int div; /* 4 x czclk */ - switch (ddr_freq) { + switch (dev_priv->mem_freq) { case 800: div = 10; break; @@ -5964,15 +5958,15 @@ int vlv_gpu_freq(int ddr_freq, int val) return -1; } - return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div); + return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); } -int vlv_freq_opcode(int ddr_freq, int val) +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) { int mul; /* 4 x czclk */ - switch (ddr_freq) { + switch (dev_priv->mem_freq) { case 800: mul = 10; break; @@ -5986,7 +5980,7 @@ int vlv_freq_opcode(int ddr_freq, int val) return -1; } - return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6; + return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; } void intel_pm_init(struct drm_device *dev) -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] drm/i915: Pass dev_priv to vlv_gpu_freq() and vlv_freq_opcode() 2013-11-05 20:42 ` [PATCH 2/4] drm/i915: Pass dev_priv to " ville.syrjala @ 2013-11-05 21:01 ` Jesse Barnes 2013-11-06 17:06 ` Daniel Vetter 0 siblings, 1 reply; 13+ messages in thread From: Jesse Barnes @ 2013-11-05 21:01 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, 5 Nov 2013 22:42:29 +0200 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We'll be looking at more than just mem_freq from dev_priv, so > just pass the whole thing. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++---------- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_sysfs.c | 13 ++++++------- > drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++--------------------- > 4 files changed, 31 insertions(+), 41 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 7008aac..9770c2f 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -974,15 +974,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) > > val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); > seq_printf(m, "max GPU freq: %d MHz\n", > - vlv_gpu_freq(dev_priv->mem_freq, val)); > + vlv_gpu_freq(dev_priv, val)); > > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); > seq_printf(m, "min GPU freq: %d MHz\n", > - vlv_gpu_freq(dev_priv->mem_freq, val)); > + vlv_gpu_freq(dev_priv, val)); > > seq_printf(m, "current GPU freq: %d MHz\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - (freq_sts >> 8) & 0xff)); > + vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); > mutex_unlock(&dev_priv->rps.hw_lock); > } else { > seq_puts(m, "no P-state info available\n"); > @@ -2725,8 +2724,7 @@ i915_max_freq_get(void *data, u64 *val) > return ret; > > if (IS_VALLEYVIEW(dev)) > - *val = vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.max_delay); > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); > else > *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; > mutex_unlock(&dev_priv->rps.hw_lock); > @@ -2756,7 +2754,7 @@ i915_max_freq_set(void *data, u64 val) > * Turbo will still be enabled, but won't go above the set value. > */ > if (IS_VALLEYVIEW(dev)) { > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > + val = vlv_freq_opcode(dev_priv, val); > dev_priv->rps.max_delay = val; > gen6_set_rps(dev, val); > } else { > @@ -2791,8 +2789,7 @@ i915_min_freq_get(void *data, u64 *val) > return ret; > > if (IS_VALLEYVIEW(dev)) > - *val = vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.min_delay); > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); > else > *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; > mutex_unlock(&dev_priv->rps.hw_lock); > @@ -2822,7 +2819,7 @@ i915_min_freq_set(void *data, u64 val) > * Turbo will still be enabled, but won't go below the set value. > */ > if (IS_VALLEYVIEW(dev)) { > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > + val = vlv_freq_opcode(dev_priv, val); > dev_priv->rps.min_delay = val; > valleyview_set_rps(dev, val); > } else { > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2aa7053..4bae871 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2412,8 +2412,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, > void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, > enum intel_sbi_destination destination); > > -int vlv_gpu_freq(int ddr_freq, int val); > -int vlv_freq_opcode(int ddr_freq, int val); > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); > > #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) > #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c > index cef38fd..5e81cf1 100644 > --- a/drivers/gpu/drm/i915/i915_sysfs.c > +++ b/drivers/gpu/drm/i915/i915_sysfs.c > @@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, > if (IS_VALLEYVIEW(dev_priv->dev)) { > u32 freq; > freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > - ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); > + ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); > } else { > ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; > } > @@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, > struct drm_i915_private *dev_priv = dev->dev_private; > > return snprintf(buf, PAGE_SIZE, "%d\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.rpe_delay)); > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay)); > } > > static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) > @@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute > > mutex_lock(&dev_priv->rps.hw_lock); > if (IS_VALLEYVIEW(dev_priv->dev)) > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay); > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); > else > ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; > mutex_unlock(&dev_priv->rps.hw_lock); > @@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, > mutex_lock(&dev_priv->rps.hw_lock); > > if (IS_VALLEYVIEW(dev_priv->dev)) { > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > + val = vlv_freq_opcode(dev_priv, val); > > hw_max = valleyview_rps_max_freq(dev_priv); > hw_min = valleyview_rps_min_freq(dev_priv); > @@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute > > mutex_lock(&dev_priv->rps.hw_lock); > if (IS_VALLEYVIEW(dev_priv->dev)) > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay); > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); > else > ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; > mutex_unlock(&dev_priv->rps.hw_lock); > @@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, > mutex_lock(&dev_priv->rps.hw_lock); > > if (IS_VALLEYVIEW(dev)) { > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > + val = vlv_freq_opcode(dev_priv, val); > > hw_max = valleyview_rps_max_freq(dev_priv); > hw_min = valleyview_rps_min_freq(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 865035b..f5bb9b3 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3609,9 +3609,9 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv) > > if (pval != dev_priv->rps.cur_delay) > DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > dev_priv->rps.cur_delay, > - vlv_gpu_freq(dev_priv->mem_freq, pval), pval); > + vlv_gpu_freq(dev_priv, pval), pval); > > dev_priv->rps.cur_delay = pval; > } > @@ -3629,10 +3629,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) > vlv_update_rps_cur_delay(dev_priv); > > DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.cur_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > dev_priv->rps.cur_delay, > - vlv_gpu_freq(dev_priv->mem_freq, val), val); > + vlv_gpu_freq(dev_priv, val), val); > > if (val == dev_priv->rps.cur_delay) > return; > @@ -3641,7 +3640,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) > > dev_priv->rps.cur_delay = val; > > - trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); > + trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); > } > > static void gen6_disable_rps_interrupts(struct drm_device *dev) > @@ -4070,32 +4069,27 @@ static void valleyview_enable_rps(struct drm_device *dev) > > dev_priv->rps.cur_delay = (val >> 8) & 0xff; > DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.cur_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > dev_priv->rps.cur_delay); > > dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); > dev_priv->rps.hw_max = dev_priv->rps.max_delay; > DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.max_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay), > dev_priv->rps.max_delay); > > dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); > DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.rpe_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > dev_priv->rps.rpe_delay); > > dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); > DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.min_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay), > dev_priv->rps.min_delay); > > DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", > - vlv_gpu_freq(dev_priv->mem_freq, > - dev_priv->rps.rpe_delay), > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > dev_priv->rps.rpe_delay); > > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > @@ -5945,12 +5939,12 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > return 0; > } > > -int vlv_gpu_freq(int ddr_freq, int val) > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > { > int div; > > /* 4 x czclk */ > - switch (ddr_freq) { > + switch (dev_priv->mem_freq) { > case 800: > div = 10; > break; > @@ -5964,15 +5958,15 @@ int vlv_gpu_freq(int ddr_freq, int val) > return -1; > } > > - return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div); > + return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); > } > > -int vlv_freq_opcode(int ddr_freq, int val) > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) > { > int mul; > > /* 4 x czclk */ > - switch (ddr_freq) { > + switch (dev_priv->mem_freq) { > case 800: > mul = 10; > break; > @@ -5986,7 +5980,7 @@ int vlv_freq_opcode(int ddr_freq, int val) > return -1; > } > > - return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6; > + return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; > } > > void intel_pm_init(struct drm_device *dev) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] drm/i915: Pass dev_priv to vlv_gpu_freq() and vlv_freq_opcode() 2013-11-05 21:01 ` Jesse Barnes @ 2013-11-06 17:06 ` Daniel Vetter 0 siblings, 0 replies; 13+ messages in thread From: Daniel Vetter @ 2013-11-06 17:06 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Nov 05, 2013 at 01:01:47PM -0800, Jesse Barnes wrote: > On Tue, 5 Nov 2013 22:42:29 +0200 > ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We'll be looking at more than just mem_freq from dev_priv, so > > just pass the whole thing. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> First two patches in this series merged to dinq, thanks. -Daniel > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++---------- > > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > > drivers/gpu/drm/i915/i915_sysfs.c | 13 ++++++------- > > drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++--------------------- > > 4 files changed, 31 insertions(+), 41 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index 7008aac..9770c2f 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -974,15 +974,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) > > > > val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); > > seq_printf(m, "max GPU freq: %d MHz\n", > > - vlv_gpu_freq(dev_priv->mem_freq, val)); > > + vlv_gpu_freq(dev_priv, val)); > > > > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); > > seq_printf(m, "min GPU freq: %d MHz\n", > > - vlv_gpu_freq(dev_priv->mem_freq, val)); > > + vlv_gpu_freq(dev_priv, val)); > > > > seq_printf(m, "current GPU freq: %d MHz\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - (freq_sts >> 8) & 0xff)); > > + vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); > > mutex_unlock(&dev_priv->rps.hw_lock); > > } else { > > seq_puts(m, "no P-state info available\n"); > > @@ -2725,8 +2724,7 @@ i915_max_freq_get(void *data, u64 *val) > > return ret; > > > > if (IS_VALLEYVIEW(dev)) > > - *val = vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.max_delay); > > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); > > else > > *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; > > mutex_unlock(&dev_priv->rps.hw_lock); > > @@ -2756,7 +2754,7 @@ i915_max_freq_set(void *data, u64 val) > > * Turbo will still be enabled, but won't go above the set value. > > */ > > if (IS_VALLEYVIEW(dev)) { > > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > > + val = vlv_freq_opcode(dev_priv, val); > > dev_priv->rps.max_delay = val; > > gen6_set_rps(dev, val); > > } else { > > @@ -2791,8 +2789,7 @@ i915_min_freq_get(void *data, u64 *val) > > return ret; > > > > if (IS_VALLEYVIEW(dev)) > > - *val = vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.min_delay); > > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); > > else > > *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; > > mutex_unlock(&dev_priv->rps.hw_lock); > > @@ -2822,7 +2819,7 @@ i915_min_freq_set(void *data, u64 val) > > * Turbo will still be enabled, but won't go below the set value. > > */ > > if (IS_VALLEYVIEW(dev)) { > > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > > + val = vlv_freq_opcode(dev_priv, val); > > dev_priv->rps.min_delay = val; > > valleyview_set_rps(dev, val); > > } else { > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 2aa7053..4bae871 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2412,8 +2412,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, > > void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, > > enum intel_sbi_destination destination); > > > > -int vlv_gpu_freq(int ddr_freq, int val); > > -int vlv_freq_opcode(int ddr_freq, int val); > > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); > > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); > > > > #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) > > #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) > > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c > > index cef38fd..5e81cf1 100644 > > --- a/drivers/gpu/drm/i915/i915_sysfs.c > > +++ b/drivers/gpu/drm/i915/i915_sysfs.c > > @@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, > > if (IS_VALLEYVIEW(dev_priv->dev)) { > > u32 freq; > > freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > - ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); > > + ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); > > } else { > > ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; > > } > > @@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > return snprintf(buf, PAGE_SIZE, "%d\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.rpe_delay)); > > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay)); > > } > > > > static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) > > @@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute > > > > mutex_lock(&dev_priv->rps.hw_lock); > > if (IS_VALLEYVIEW(dev_priv->dev)) > > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay); > > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); > > else > > ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; > > mutex_unlock(&dev_priv->rps.hw_lock); > > @@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, > > mutex_lock(&dev_priv->rps.hw_lock); > > > > if (IS_VALLEYVIEW(dev_priv->dev)) { > > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > > + val = vlv_freq_opcode(dev_priv, val); > > > > hw_max = valleyview_rps_max_freq(dev_priv); > > hw_min = valleyview_rps_min_freq(dev_priv); > > @@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute > > > > mutex_lock(&dev_priv->rps.hw_lock); > > if (IS_VALLEYVIEW(dev_priv->dev)) > > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay); > > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); > > else > > ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; > > mutex_unlock(&dev_priv->rps.hw_lock); > > @@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, > > mutex_lock(&dev_priv->rps.hw_lock); > > > > if (IS_VALLEYVIEW(dev)) { > > - val = vlv_freq_opcode(dev_priv->mem_freq, val); > > + val = vlv_freq_opcode(dev_priv, val); > > > > hw_max = valleyview_rps_max_freq(dev_priv); > > hw_min = valleyview_rps_min_freq(dev_priv); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 865035b..f5bb9b3 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3609,9 +3609,9 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv) > > > > if (pval != dev_priv->rps.cur_delay) > > DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > > dev_priv->rps.cur_delay, > > - vlv_gpu_freq(dev_priv->mem_freq, pval), pval); > > + vlv_gpu_freq(dev_priv, pval), pval); > > > > dev_priv->rps.cur_delay = pval; > > } > > @@ -3629,10 +3629,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) > > vlv_update_rps_cur_delay(dev_priv); > > > > DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.cur_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > > dev_priv->rps.cur_delay, > > - vlv_gpu_freq(dev_priv->mem_freq, val), val); > > + vlv_gpu_freq(dev_priv, val), val); > > > > if (val == dev_priv->rps.cur_delay) > > return; > > @@ -3641,7 +3640,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) > > > > dev_priv->rps.cur_delay = val; > > > > - trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); > > + trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); > > } > > > > static void gen6_disable_rps_interrupts(struct drm_device *dev) > > @@ -4070,32 +4069,27 @@ static void valleyview_enable_rps(struct drm_device *dev) > > > > dev_priv->rps.cur_delay = (val >> 8) & 0xff; > > DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.cur_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), > > dev_priv->rps.cur_delay); > > > > dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); > > dev_priv->rps.hw_max = dev_priv->rps.max_delay; > > DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.max_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay), > > dev_priv->rps.max_delay); > > > > dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); > > DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.rpe_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > > dev_priv->rps.rpe_delay); > > > > dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); > > DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.min_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay), > > dev_priv->rps.min_delay); > > > > DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv->mem_freq, > > - dev_priv->rps.rpe_delay), > > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > > dev_priv->rps.rpe_delay); > > > > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > > @@ -5945,12 +5939,12 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > > return 0; > > } > > > > -int vlv_gpu_freq(int ddr_freq, int val) > > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > > { > > int div; > > > > /* 4 x czclk */ > > - switch (ddr_freq) { > > + switch (dev_priv->mem_freq) { > > case 800: > > div = 10; > > break; > > @@ -5964,15 +5958,15 @@ int vlv_gpu_freq(int ddr_freq, int val) > > return -1; > > } > > > > - return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div); > > + return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); > > } > > > > -int vlv_freq_opcode(int ddr_freq, int val) > > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) > > { > > int mul; > > > > /* 4 x czclk */ > > - switch (ddr_freq) { > > + switch (dev_priv->mem_freq) { > > case 800: > > mul = 10; > > break; > > @@ -5986,7 +5980,7 @@ int vlv_freq_opcode(int ddr_freq, int val) > > return -1; > > } > > > > - return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6; > > + return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; > > } > > > > void intel_pm_init(struct drm_device *dev) > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > -- > Jesse Barnes, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV 2013-11-05 20:42 [PATCH 0/4] drm/i915: VLV graphics clock improvements ville.syrjala 2013-11-05 20:42 ` [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() ville.syrjala 2013-11-05 20:42 ` [PATCH 2/4] drm/i915: Pass dev_priv to " ville.syrjala @ 2013-11-05 20:42 ` ville.syrjala 2013-11-05 21:02 ` Jesse Barnes 2013-11-05 20:42 ` [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass ville.syrjala 3 siblings, 1 reply; 13+ messages in thread From: ville.syrjala @ 2013-11-05 20:42 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Keep the HPLL frequencey in dev_priv on VLV instead of reading it from CCK every time it's needed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4bae871..dd40925 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1360,7 +1360,7 @@ typedef struct drm_i915_private { int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */ - unsigned int fsb_freq, mem_freq, is_ddr3; + unsigned int fsb_freq, mem_freq, is_ddr3, hpll_vco; /** * wq - Driver workqueue for GEM. diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 48f4990..f97e895 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3898,13 +3898,18 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv) { int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; + if (dev_priv->hpll_vco) + return dev_priv->hpll_vco; + /* Obtain SKU information */ mutex_lock(&dev_priv->dpio_lock); hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; mutex_unlock(&dev_priv->dpio_lock); - return vco_freq[hpll_freq]; + dev_priv->hpll_vco = vco_freq[hpll_freq]; + + return dev_priv->hpll_vco; } /* Adjust CDclk dividers to allow high res or save power if possible */ -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV 2013-11-05 20:42 ` [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV ville.syrjala @ 2013-11-05 21:02 ` Jesse Barnes 2013-11-06 8:41 ` Ville Syrjälä 0 siblings, 1 reply; 13+ messages in thread From: Jesse Barnes @ 2013-11-05 21:02 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, 5 Nov 2013 22:42:30 +0200 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Keep the HPLL frequencey in dev_priv on VLV instead of reading > it from CCK every time it's needed. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/intel_display.c | 7 ++++++- > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4bae871..dd40925 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1360,7 +1360,7 @@ typedef struct drm_i915_private { > int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ > int num_fence_regs; /* 8 on pre-965, 16 otherwise */ > > - unsigned int fsb_freq, mem_freq, is_ddr3; > + unsigned int fsb_freq, mem_freq, is_ddr3, hpll_vco; > > /** > * wq - Driver workqueue for GEM. > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 48f4990..f97e895 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3898,13 +3898,18 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv) > { > int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; > > + if (dev_priv->hpll_vco) > + return dev_priv->hpll_vco; > + > /* Obtain SKU information */ > mutex_lock(&dev_priv->dpio_lock); > hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & > CCK_FUSE_HPLL_FREQ_MASK; > mutex_unlock(&dev_priv->dpio_lock); > > - return vco_freq[hpll_freq]; > + dev_priv->hpll_vco = vco_freq[hpll_freq]; > + > + return dev_priv->hpll_vco; > } > > /* Adjust CDclk dividers to allow high res or save power if possible */ I'd just move this to init_clock_gating or something, then use dev_priv->hpll_vco everywhere, rather than this conditional lazy initialization. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV 2013-11-05 21:02 ` Jesse Barnes @ 2013-11-06 8:41 ` Ville Syrjälä 2013-11-06 10:02 ` Daniel Vetter 0 siblings, 1 reply; 13+ messages in thread From: Ville Syrjälä @ 2013-11-06 8:41 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Nov 05, 2013 at 01:02:58PM -0800, Jesse Barnes wrote: > On Tue, 5 Nov 2013 22:42:30 +0200 > ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Keep the HPLL frequencey in dev_priv on VLV instead of reading > > it from CCK every time it's needed. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > drivers/gpu/drm/i915/intel_display.c | 7 ++++++- > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 4bae871..dd40925 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1360,7 +1360,7 @@ typedef struct drm_i915_private { > > int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ > > int num_fence_regs; /* 8 on pre-965, 16 otherwise */ > > > > - unsigned int fsb_freq, mem_freq, is_ddr3; > > + unsigned int fsb_freq, mem_freq, is_ddr3, hpll_vco; > > > > /** > > * wq - Driver workqueue for GEM. > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 48f4990..f97e895 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -3898,13 +3898,18 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv) > > { > > int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; > > > > + if (dev_priv->hpll_vco) > > + return dev_priv->hpll_vco; > > + > > /* Obtain SKU information */ > > mutex_lock(&dev_priv->dpio_lock); > > hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & > > CCK_FUSE_HPLL_FREQ_MASK; > > mutex_unlock(&dev_priv->dpio_lock); > > > > - return vco_freq[hpll_freq]; > > + dev_priv->hpll_vco = vco_freq[hpll_freq]; > > + > > + return dev_priv->hpll_vco; > > } > > > > /* Adjust CDclk dividers to allow high res or save power if possible */ > > I'd just move this to init_clock_gating or something, then use > dev_priv->hpll_vco everywhere, rather than this conditional lazy > initialization. The problem was the we need it at gmbus init time, and we do that very early. So I couldn't figure out a nice place to stick it, and so I ended up doing the lazy thing. I suspect the best thing to do would be to move gmbus init to happen later, alongside other modeset setup. But I'm feeling a bit lazy and don't want to tackle that task right now. Anyways, since we don't want patch 4/4, I think for now we can just drop this one as well. The places where we call it currently aren't really that frequent or performance sensitive. -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV 2013-11-06 8:41 ` Ville Syrjälä @ 2013-11-06 10:02 ` Daniel Vetter 0 siblings, 0 replies; 13+ messages in thread From: Daniel Vetter @ 2013-11-06 10:02 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Wed, Nov 06, 2013 at 10:41:22AM +0200, Ville Syrjälä wrote: > On Tue, Nov 05, 2013 at 01:02:58PM -0800, Jesse Barnes wrote: > > On Tue, 5 Nov 2013 22:42:30 +0200 > > ville.syrjala@linux.intel.com wrote: > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > Keep the HPLL frequencey in dev_priv on VLV instead of reading > > > it from CCK every time it's needed. > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > > drivers/gpu/drm/i915/intel_display.c | 7 ++++++- > > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > > index 4bae871..dd40925 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -1360,7 +1360,7 @@ typedef struct drm_i915_private { > > > int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ > > > int num_fence_regs; /* 8 on pre-965, 16 otherwise */ > > > > > > - unsigned int fsb_freq, mem_freq, is_ddr3; > > > + unsigned int fsb_freq, mem_freq, is_ddr3, hpll_vco; > > > > > > /** > > > * wq - Driver workqueue for GEM. > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > index 48f4990..f97e895 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -3898,13 +3898,18 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv) > > > { > > > int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; > > > > > > + if (dev_priv->hpll_vco) > > > + return dev_priv->hpll_vco; > > > + > > > /* Obtain SKU information */ > > > mutex_lock(&dev_priv->dpio_lock); > > > hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & > > > CCK_FUSE_HPLL_FREQ_MASK; > > > mutex_unlock(&dev_priv->dpio_lock); > > > > > > - return vco_freq[hpll_freq]; > > > + dev_priv->hpll_vco = vco_freq[hpll_freq]; > > > + > > > + return dev_priv->hpll_vco; > > > } > > > > > > /* Adjust CDclk dividers to allow high res or save power if possible */ > > > > I'd just move this to init_clock_gating or something, then use > > dev_priv->hpll_vco everywhere, rather than this conditional lazy > > initialization. > > The problem was the we need it at gmbus init time, and we do that very > early. So I couldn't figure out a nice place to stick it, and so > I ended up doing the lazy thing. > > I suspect the best thing to do would be to move gmbus init to happen > later, alongside other modeset setup. But I'm feeling a bit lazy and > don't want to tackle that task right now. > > Anyways, since we don't want patch 4/4, I think for now we can just > drop this one as well. The places where we call it currently aren't > really that frequent or performance sensitive. init ordering hell strikes again. If we opt for a fixed order (the lazy ordering seems to not be too evil though in this case) I'd like to have a big WARN in there in case we get it wrong. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass 2013-11-05 20:42 [PATCH 0/4] drm/i915: VLV graphics clock improvements ville.syrjala ` (2 preceding siblings ...) 2013-11-05 20:42 ` [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV ville.syrjala @ 2013-11-05 20:42 ` ville.syrjala 2013-11-05 21:03 ` Jesse Barnes 3 siblings, 1 reply; 13+ messages in thread From: ville.syrjala @ 2013-11-05 20:42 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Supposedly all current SKUs use GPLL, but there could be ones in the future that do not. Add (at least theoretical) support for such things. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dd40925..d9b4c26 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -876,6 +876,7 @@ struct intel_gen6_power_mgmt { enum { LOW_POWER, BETWEEN, HIGH_POWER } power; bool enabled; + bool gpll_enabled; struct delayed_work delayed_resume_work; /* diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f5bb9b3..caec9fe 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4064,7 +4064,9 @@ static void valleyview_enable_rps(struct drm_device *dev) val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); + dev_priv->rps.gpll_enabled = val & 0x10; + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", + dev_priv->rps.gpll_enabled ? "yes" : "no"); DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); dev_priv->rps.cur_delay = (val >> 8) & 0xff; @@ -5943,6 +5945,17 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) { int div; + if (!dev_priv->rps.gpll_enabled) { + int hpll_freq = valleyview_get_vco(dev_priv); + + div = 0xee + (10 << 1) - val; + + if (WARN_ON(div == 0)) + return -1; + + return DIV_ROUND_CLOSEST(hpll_freq << 1, div); + } + /* 4 x czclk */ switch (dev_priv->mem_freq) { case 800: @@ -5965,6 +5978,15 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) { int mul; + if (!dev_priv->rps.gpll_enabled) { + int hpll_freq = valleyview_get_vco(dev_priv); + + if (WARN_ON(val == 0)) + return -1; + + return 0xee + (10 << 1) - DIV_ROUND_CLOSEST(hpll_freq << 1, val); + } + /* 4 x czclk */ switch (dev_priv->mem_freq) { case 800: -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass 2013-11-05 20:42 ` [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass ville.syrjala @ 2013-11-05 21:03 ` Jesse Barnes 2013-11-06 17:07 ` Daniel Vetter 0 siblings, 1 reply; 13+ messages in thread From: Jesse Barnes @ 2013-11-05 21:03 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, 5 Nov 2013 22:42:31 +0200 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Supposedly all current SKUs use GPLL, but there could be ones in the > future that do not. Add (at least theoretical) support for such things. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++++++++- > 2 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index dd40925..d9b4c26 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -876,6 +876,7 @@ struct intel_gen6_power_mgmt { > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > > bool enabled; > + bool gpll_enabled; > struct delayed_work delayed_resume_work; > > /* > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index f5bb9b3..caec9fe 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4064,7 +4064,9 @@ static void valleyview_enable_rps(struct drm_device *dev) > > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); > + dev_priv->rps.gpll_enabled = val & 0x10; > + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", > + dev_priv->rps.gpll_enabled ? "yes" : "no"); > DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); > > dev_priv->rps.cur_delay = (val >> 8) & 0xff; > @@ -5943,6 +5945,17 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > { > int div; > > + if (!dev_priv->rps.gpll_enabled) { > + int hpll_freq = valleyview_get_vco(dev_priv); > + > + div = 0xee + (10 << 1) - val; > + > + if (WARN_ON(div == 0)) > + return -1; > + > + return DIV_ROUND_CLOSEST(hpll_freq << 1, div); > + } > + > /* 4 x czclk */ > switch (dev_priv->mem_freq) { > case 800: > @@ -5965,6 +5978,15 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) > { > int mul; > > + if (!dev_priv->rps.gpll_enabled) { > + int hpll_freq = valleyview_get_vco(dev_priv); > + > + if (WARN_ON(val == 0)) > + return -1; > + > + return 0xee + (10 << 1) - DIV_ROUND_CLOSEST(hpll_freq << 1, val); > + } > + > /* 4 x czclk */ > switch (dev_priv->mem_freq) { > case 800: I don't think we want to add this; even though it's a small amount of code it's totally unnecessary on real hw, and will probably just bit rot. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass 2013-11-05 21:03 ` Jesse Barnes @ 2013-11-06 17:07 ` Daniel Vetter 0 siblings, 0 replies; 13+ messages in thread From: Daniel Vetter @ 2013-11-06 17:07 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Nov 05, 2013 at 01:03:37PM -0800, Jesse Barnes wrote: > I don't think we want to add this; even though it's a small amount of > code it's totally unnecessary on real hw, and will probably just bit > rot. Wholeheartedly agreed. Stuff that isn't used bitrots and then confuses because "this can't possibly work ... oh, unused." Sometimes the dot encompass a few months though. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2013-11-06 17:07 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-11-05 20:42 [PATCH 0/4] drm/i915: VLV graphics clock improvements ville.syrjala 2013-11-05 20:42 ` [PATCH 1/4] drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode() ville.syrjala 2013-11-06 16:56 ` Jesse Barnes 2013-11-05 20:42 ` [PATCH 2/4] drm/i915: Pass dev_priv to " ville.syrjala 2013-11-05 21:01 ` Jesse Barnes 2013-11-06 17:06 ` Daniel Vetter 2013-11-05 20:42 ` [PATCH 3/4] drm/i915: Store HPLL frequency in dev_priv on VLV ville.syrjala 2013-11-05 21:02 ` Jesse Barnes 2013-11-06 8:41 ` Ville Syrjälä 2013-11-06 10:02 ` Daniel Vetter 2013-11-05 20:42 ` [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass ville.syrjala 2013-11-05 21:03 ` Jesse Barnes 2013-11-06 17:07 ` Daniel Vetter
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox