From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register
 to be more structure to match configdb document.
Date: Thu, 7 Nov 2013 14:43:32 +0200
Message-ID: <20131107124332.GI5986@intel.com>
References: <1383102678-7150-2-git-send-email-chon.ming.lee@intel.com>
	<1383719856-28465-1-git-send-email-chon.ming.lee@intel.com>
	<20131106120224.GE5986@intel.com>
	<20131107022544.GD2637@clee30-mobl2.gar.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
	by gabe.freedesktop.org (Postfix) with ESMTP id DAF23EF6A3
	for <intel-gfx@lists.freedesktop.org>;
	Thu,  7 Nov 2013 04:43:35 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <20131107022544.GD2637@clee30-mobl2.gar.corp.intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces@lists.freedesktop.org
Errors-To: intel-gfx-bounces@lists.freedesktop.org
To: "Lee, Chon Ming" <chon.ming.lee@intel.com>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Thu, Nov 07, 2013 at 10:25:44AM +0800, Lee, Chon Ming wrote:
> On 11/06 14:02, Ville Syrj=E4l=E4 wrote:
> =

> > > -#define _DPIO_IREF_CTL_A		0x8040
> > > -#define _DPIO_IREF_CTL_B		0x8060
> > > -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF=
_CTL_B)
> > > +#define _VLV_PLL_DW10_CH0		0x8040
> > > +#define _VLV_PLL_DW10_CH1		0x8060
> > > +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_=
CH1)
> > =

> > Configdb starts counting from DW8 at 0x8040/60, which kind of make sense
> > since the first PLL block ends at DW7.
> > =

> The spreadsheet I refer to is using DW10.  The spreadsheet might be incor=
rect.
> Looking at the register offset, it won't be anymore space left after firs=
t PLL
> block.  Make sense for DW8 for second PLL block.   =


The spreadsheet is a bit weird. I was just looking at the web configdb.
That at least has some sense in the offsets (apart from the ref block).
The spreadsheet also uses hex numbers to count the dwords, which doesn't
match what you've done for the > 8 numbers. So I'd go with the web =

configdb numbers since they're a bit more consistent.

-- =

Ville Syrj=E4l=E4
Intel OTC