From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] [VPG HSW-A] drm/i915: BUN vol4g[DevHSW] Vblank interrupt on disabled pipe Date: Thu, 7 Nov 2013 14:52:55 +0200 Message-ID: <20131107125255.GK5986@intel.com> References: <1378295042-12408-1-git-send-email-sandeepx.ramakutty@intel.com> <20130904124546.GR11428@intel.com> <9FFD648774C2FE4CBFB1FC2607336026096654@BGSMSX102.gar.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 0513738C4E for ; Thu, 7 Nov 2013 04:52:59 -0800 (PST) Content-Disposition: inline In-Reply-To: <9FFD648774C2FE4CBFB1FC2607336026096654@BGSMSX102.gar.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: "Ramakutty, SandeepX" Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Thu, Nov 07, 2013 at 11:56:22AM +0000, Ramakutty, SandeepX wrote: > Hi Ville, > = > Thanks for the feedback. > = > The BUN indicates this as a workaround for hardware limitation. It specif= ies that if the interrupt is not disabled on a pipe that is disabled, the s= ystem will not go to C3 state. This affects situations when only edp is con= nected and hdmi is not connected. That is Pipe B is disabled. Since this i= s generic for all haswell platforms not sure whether non Android systems go= es to the C3 state if the BUN is not implemented. > = > Details can be found in North Display Engine Registers-> North Display En= gine Shared Functions -> Interrupts = It says "enabled and _unmasked_". We mask it, so there's no problem. > = > Regards, > Sandeep > = > -----Original Message----- > From: Ville Syrj=E4l=E4 [mailto:ville.syrjala@linux.intel.com] = > Sent: Wednesday, September 04, 2013 6:16 PM > To: Ramakutty, SandeepX > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] [VPG HSW-A] drm/i915: BUN vol4g[DevHSW] = Vblank interrupt on disabled pipe > = > On Wed, Sep 04, 2013 at 05:14:02PM +0530, Sandeep Ramankutty wrote: > > This change is to comply with the BUN - Vblank interrupt on disabled pi= pe. > > BUN states - Do not unmask and enable a vertical blank interrupt on a = > > pipe that is not enabled. Do not leave this interrupt enabled and = > > unmasked after the associated pipe is disabled. If the vblank = > > interrupt is unmasked and enabled on a disabled pipe it will block pack= age C3, wasting power. > = > We mask the interrupt in IMR when we don't need it, but we do leave it en= abled in IER. Is that a problem on HSW? I'm guessing not, since powertop is= telling me that I'm currently reaching pc8 w/ displays off, and pc7 w/ eDP= on. > = > In any case the patch would be buggy since it has no locking around DEIER= RMW accesses. But since powertop is telling me everything is already fine,= we shouldn't need this patch anyway. > = > -- > Ville Syrj=E4l=E4 > Intel OTC -- = Ville Syrj=E4l=E4 Intel OTC