From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Fix up the bdw pipe interrupt enable lists Date: Thu, 7 Nov 2013 16:00:18 +0200 Message-ID: <20131107140018.GS5986@intel.com> References: <1383818746-1199-2-git-send-email-daniel.vetter@ffwll.ch> <1383832164-16998-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id A2B60EF36B for ; Thu, 7 Nov 2013 06:01:49 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383832164-16998-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Nov 07, 2013 at 02:49:24PM +0100, Daniel Vetter wrote: > - Pipe underrun can't just be enabled, we need some support code like > on ilk-hsw to make this happen. So drop it for now. > - CRC error is a special mode of the CRC hardware that we don't use, > so again drop it. Real CRC support for bdw will be added later. > - All the other error bits are about faults, so rename the #define and > adjust the output. > = > v2: Use pipe_name as pointed out by Ville. Ville's comment was on a > previous patch, but it was easier to squash in here. > = > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_irq.c | 10 ++++++---- > drivers/gpu/drm/i915/i915_reg.h | 9 ++++----- > 2 files changed, 10 insertions(+), 9 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index c04fbbf0acf7..e1bfc85d1789 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1793,8 +1793,11 @@ static irqreturn_t gen8_irq_handler(int irq, void = *arg) > intel_finish_page_flip_plane(dev, pipe); > } > = > - if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS) > - DRM_ERROR("Errors on pipe %c\n", 'A' + pipe); > + if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { > + DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", > + pipe_name(pipe), > + pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); > + } > = > if (pipe_iir) { > ret =3D IRQ_HANDLED; > @@ -2863,9 +2866,8 @@ static void gen8_de_irq_postinstall(struct drm_i915= _private *dev_priv) > { > struct drm_device *dev =3D dev_priv->dev; > uint32_t de_pipe_enables =3D GEN8_PIPE_FLIP_DONE | > - GEN8_PIPE_SCAN_LINE_EVENT | > GEN8_PIPE_VBLANK | > - GEN8_DE_PIPE_IRQ_ERRORS; > + GEN8_DE_PIPE_IRQ_FAULT_ERRORS; > int pipe; > dev_priv->de_irq_mask[PIPE_A] =3D ~de_pipe_enables; > dev_priv->de_irq_mask[PIPE_B] =3D ~de_pipe_enables; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index f150edaa64ca..9e7588345017 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4064,11 +4064,10 @@ > #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) > #define GEN8_PIPE_VSYNC (1 << 1) > #define GEN8_PIPE_VBLANK (1 << 0) > -#define GEN8_DE_PIPE_IRQ_ERRORS (GEN8_PIPE_UNDERRUN | \ > - GEN8_PIPE_CDCLK_CRC_ERROR | \ > - GEN8_PIPE_CURSOR_FAULT | \ > - GEN8_PIPE_SPRITE_FAULT | \ > - GEN8_PIPE_PRIMARY_FAULT) > +#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ > + (GEN8_PIPE_CURSOR_FAULT | \ > + GEN8_PIPE_SPRITE_FAULT | \ > + GEN8_PIPE_PRIMARY_FAULT) > = > #define GEN8_DE_PORT_ISR 0x44440 > #define GEN8_DE_PORT_IMR 0x44444 > -- = > 1.8.4.rc3 -- = Ville Syrj=E4l=E4 Intel OTC