From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/2] drm/i915: Mask the vblank interrupt on bdw by default Date: Thu, 7 Nov 2013 16:35:44 +0200 Message-ID: <20131107143544.GW5986@intel.com> References: <20131107133754.GO5986@intel.com> <1383834713-3153-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 3745138DF8 for ; Thu, 7 Nov 2013 06:35:49 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383834713-3153-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Nov 07, 2013 at 03:31:52PM +0100, Daniel Vetter wrote: > Reported-by: Ville Syrj=E4l=E4 > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index bf71e352fd74..1ce5722c2462 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2917,15 +2917,15 @@ static void gen8_gt_irq_postinstall(struct drm_i9= 15_private *dev_priv) > static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > { > struct drm_device *dev =3D dev_priv->dev; > - uint32_t de_pipe_enables =3D GEN8_PIPE_FLIP_DONE | > - GEN8_PIPE_VBLANK | > - GEN8_PIPE_CDCLK_CRC_DONE | > - GEN8_PIPE_FIFO_UNDERRUN | > - GEN8_DE_PIPE_IRQ_FAULT_ERRORS; > + uint32_t de_pipe_masked =3D GEN8_PIPE_FLIP_DONE | > + GEN8_PIPE_CDCLK_CRC_DONE | > + GEN8_PIPE_FIFO_UNDERRUN | > + GEN8_DE_PIPE_IRQ_FAULT_ERRORS; > + uint32_t de_pipe_enables =3D de_pipe_masked | GEN8_PIPE_VBLANK; > int pipe; > - dev_priv->de_irq_mask[PIPE_A] =3D ~de_pipe_enables; > - dev_priv->de_irq_mask[PIPE_B] =3D ~de_pipe_enables; > - dev_priv->de_irq_mask[PIPE_C] =3D ~de_pipe_enables; > + dev_priv->de_irq_mask[PIPE_A] =3D ~de_pipe_masked; > + dev_priv->de_irq_mask[PIPE_B] =3D ~de_pipe_masked; > + dev_priv->de_irq_mask[PIPE_C] =3D ~de_pipe_masked; > = > for_each_pipe(pipe) { > u32 tmp =3D I915_READ(GEN8_DE_PIPE_IIR(pipe)); > -- = > 1.8.4.rc3 -- = Ville Syrj=E4l=E4 Intel OTC