From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 05/10] drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRI Date: Wed, 20 Nov 2013 14:50:15 -0800 Message-ID: <20131120225015.GC4234@bratislava.jf.intel.com> References: <1383771745-22463-1-git-send-email-ville.syrjala@linux.intel.com> <1383771745-22463-6-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-pd0-f175.google.com (mail-pd0-f175.google.com [209.85.192.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 07B4FFBE0A for ; Wed, 20 Nov 2013 14:50:15 -0800 (PST) Received: by mail-pd0-f175.google.com with SMTP id w10so8157287pde.34 for ; Wed, 20 Nov 2013 14:50:14 -0800 (PST) Content-Disposition: inline In-Reply-To: <1383771745-22463-6-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Reviewed-by: Rodrigo Vivi On Wed, Nov 06, 2013 at 11:02:20PM +0200, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > The spec tells us that we need to emit an SRM after the LRI > to MSG_FBC_REND_STATE. > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++-- > 2 files changed, 5 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 0719c8b..7a4d3e1 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -235,6 +235,7 @@ > */ > #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) > #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) > +#define MI_SRM_LRM_GLOBAL_GTT (1<<22) > #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ > #define MI_FLUSH_DW_STORE_INDEX (1<<21) > #define MI_INVALIDATE_TLB (1<<18) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 752f208..4649bf5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_bu= ffer *ring, u32 value) > if (!ring->fbc_dirty) > return 0; > = > - ret =3D intel_ring_begin(ring, 4); > + ret =3D intel_ring_begin(ring, 6); > if (ret) > return ret; > - intel_ring_emit(ring, MI_NOOP); > /* WaFbcNukeOn3DBlt:ivb/hsw */ > intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); > intel_ring_emit(ring, MSG_FBC_REND_STATE); > intel_ring_emit(ring, value); > + intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); > + intel_ring_emit(ring, MSG_FBC_REND_STATE); > + intel_ring_emit(ring, ring->scratch.gtt_offset + 256); > intel_ring_advance(ring); > = > ring->fbc_dirty =3D false; > -- = > 1.8.1.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx