From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/3] drm/i915/vlv: Valleyview support for forcewake Individual power wells. Date: Mon, 25 Nov 2013 08:36:59 -0800 Message-ID: <20131125083659.623381d2@jbarnes-desktop> References: <1385198744-9333-1-git-send-email-deepak.s@intel.com> <1385198744-9333-3-git-send-email-deepak.s@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy18-pub.mail.unifiedlayer.com (oproxy18-pub.mail.unifiedlayer.com [69.89.17.20]) by gabe.freedesktop.org (Postfix) with SMTP id 806E2FA8CC for ; Mon, 25 Nov 2013 08:35:42 -0800 (PST) In-Reply-To: <1385198744-9333-3-git-send-email-deepak.s@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 23 Nov 2013 14:55:43 +0530 deepak.s@intel.com wrote: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9292c9e..04d46b2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4840,8 +4840,8 @@ > #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) > > #define FORCEWAKE 0xA18C > -#define FORCEWAKE_VLV 0x1300b0 > -#define FORCEWAKE_ACK_VLV 0x1300b4 > +#define FORCEWAKE_VLV 0x1300b0 > +#define FORCEWAKE_ACK_VLV 0x1300b4 > #define FORCEWAKE_MEDIA_VLV 0x1300b8 > #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc > #define FORCEWAKE_ACK_HSW 0x130044 Another spurious hunk, but again maybe Daniel can drop it. I'd have structured the force wake callbacks a little differently (still used the vfunc then split the routines into separate _locked variants for each of render and media), but that's just cosmetic. So: Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center