From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 1/9] drm/i915: Don't set the fence number in
 DPFC_CTL on SNB
Date: Mon, 25 Nov 2013 09:43:36 +0100
Message-ID: <20131125084336.GS27344@phenom.ffwll.local>
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To: Chris Wilson <chris@chris-wilson.co.uk>, ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
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On Thu, Nov 21, 2013 at 11:22:14PM +0000, Chris Wilson wrote:
> On Thu, Nov 21, 2013 at 09:29:45PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > SNB has another register where the actual FBC CPU fence number is
> > stored. The documenation explicitly states that the fence number
> > in DPFC_CTL must be 0 on SNB. And in fact when it's not zero,
> > the GTT tracking simply doesn't work.
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch