From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 9/9] drm/i915: Flush caches for scanout
 during cpu->gtt move
Date: Mon, 25 Nov 2013 09:47:28 +0100
Message-ID: <20131125084728.GU27344@phenom.ffwll.local>
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To: Chris Wilson <chris@chris-wilson.co.uk>, ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
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On Thu, Nov 21, 2013 at 11:20:58PM +0000, Chris Wilson wrote:
> On Thu, Nov 21, 2013 at 09:29:53PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Flush the caches when moving a scanout buffer from CPU to GTT domain.
> > This allows us to move a scanout buffer to CPU write domain, do some
> > writes, and move it back to the GTT read domain. The display will then
> > see the correct data. In addition we still need to do the dirtyfb
> > ioctl to nuke FBC if that's enabled.
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Isn't this what sw_finish is for?
> =

> But we could actually rework flush_cpu_write_domain to drop the force
> parameter now that we have obj->pin_display.

Although it doesn't really fit into the new world any longer ...
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch