From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Prefer setting PTE cache age to 3
Date: Mon, 25 Nov 2013 09:50:49 +0100
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To: Eric Anholt <eric@anholt.net>
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On Fri, Nov 22, 2013 at 10:38:41AM -0800, Eric Anholt wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > We have conflicting benchmark data that suggest either age 0 or age 3 is
> > better. However, the earlier benchmark on which we based the switch to
> > age 0
> >
> > (commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
> > Author: Ben Widawsky <benjamin.widawsky@intel.com>
> > Date:   Thu Jul 4 11:02:03 2013 -0700
> >
> >     drm/i915/hsw: Set correct Haswell PTE encodings)
> >
> > actually seems to prefer the default PTE encoding as age 3. Presumably,
> > this is in part due to the use of MOCS to override the PTE encodings
> > when appropriate.
> 
> This bothered me when reviewing the kernel code for hsw.  Thanks.
> 
> Reviewed-by: Eric Anholt <eric@anholt.net>
> 
> Note that userspace doesn't currently set MOCS other than the L3 bit.
> I'm hoping we end up not having to, since we don't have a WT option in
> MOCS other than "just listen to the PTEs".

Picked up for -fixes, thanks for the patch&review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch