From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 9/9] drm/i915: Flush caches for scanout
 during cpu->gtt move
Date: Mon, 25 Nov 2013 16:40:22 +0200
Message-ID: <20131125144022.GQ10036@intel.com>
References: <1385062193-19466-1-git-send-email-ville.syrjala@linux.intel.com>
	<1385062193-19466-10-git-send-email-ville.syrjala@linux.intel.com>
	<20131121232058.GB4166@nuc-i3427.alporthouse.com>
	<20131125084728.GU27344@phenom.ffwll.local>
	<20131125110448.GD21316@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
	by gabe.freedesktop.org (Postfix) with ESMTP id 3F472FA4E5
	for <intel-gfx@lists.freedesktop.org>;
	Mon, 25 Nov 2013 06:40:30 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <20131125110448.GD21316@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces@lists.freedesktop.org
Errors-To: intel-gfx-bounces@lists.freedesktop.org
To: Chris Wilson <chris@chris-wilson.co.uk>, Daniel Vetter <daniel@ffwll.ch>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Mon, Nov 25, 2013 at 11:04:48AM +0000, Chris Wilson wrote:
> On Mon, Nov 25, 2013 at 09:47:28AM +0100, Daniel Vetter wrote:
> > On Thu, Nov 21, 2013 at 11:20:58PM +0000, Chris Wilson wrote:
> > > On Thu, Nov 21, 2013 at 09:29:53PM +0200, ville.syrjala@linux.intel.c=
om wrote:
> > > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > > =

> > > > Flush the caches when moving a scanout buffer from CPU to GTT domai=
n.
> > > > This allows us to move a scanout buffer to CPU write domain, do some
> > > > writes, and move it back to the GTT read domain. The display will t=
hen
> > > > see the correct data. In addition we still need to do the dirtyfb
> > > > ioctl to nuke FBC if that's enabled.
> > > > =

> > > > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > =

> > Isn't this what sw_finish is for?
> =

> I was more concerned about making sure the code was reasonably
> self-consistent in applying our own coherency rules. As you point out,
> it may be userspace making a mistake, but so many paths can end up here,
> and almost never have pin_display, that it would seem to be preferrable
> to do the extra flush rather than have the discrepancy.

If we don't do the flush in CPU->GTT move, we might miss it completely.
Eg. if we do things in this order:

set_domain(CPU,CPU)
write some data
set_domain(GTT,0)
sw_finish()

sw_finish would not do the flush since the object is no longer in the
CPU write domain.

-- =

Ville Syrj=E4l=E4
Intel OTC