From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: 3.13-rc2, i855, [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.crtc_clock Date: Thu, 5 Dec 2013 12:49:56 +0200 Message-ID: <20131205104956.GX10036@intel.com> References: <20131204210922.0dc90878@neptune.home> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D7B7FB27F for ; Thu, 5 Dec 2013 02:50:05 -0800 (PST) Content-Disposition: inline In-Reply-To: <20131204210922.0dc90878@neptune.home> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Bruno =?iso-8859-1?Q?Pr=E9mont?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Dec 04, 2013 at 09:09:22PM +0100, Bruno Pr=E9mont wrote: > [ 1.621199] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjust= ed_mode.crtc_clock (expected 108000, found 48000) Hmm. Kind of looks like we're reading/parsing the PLL registers incorrectly. Let's try to see what the driver thinks the registers contain: >>From 4a804c01e051b2cb853d3d5114ae77d1646fb889 Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?Ville=3D20Syrj=3DC3=3DA4l=3DC3=3DA4?=3D Date: Thu, 5 Dec 2013 12:44:27 +0200 Subject: [PATCH] dpll state debug --- drivers/gpu/drm/i915/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/in= tel_display.c index 3f2f1d2..b8f9077 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8976,6 +8976,10 @@ static void intel_dump_pipe_config(struct intel_crtc= *crtc, pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); + DRM_DEBUG_KMS("DPLL =3D 0x%x\n", pipe_config->dpll_hw_state.dpll); + DRM_DEBUG_KMS("DPLL_MD =3D 0x%x\n", pipe_config->dpll_hw_state.dpll_md); + DRM_DEBUG_KMS("FP0 =3D 0x%x\n", pipe_config->dpll_hw_state.fp0); + DRM_DEBUG_KMS("FP1 =3D 0x%x\n", pipe_config->dpll_hw_state.fp1); } = static bool check_encoder_cloning(struct drm_crtc *crtc) -- = 1.8.3.2 -- = Ville Syrj=E4l=E4 Intel OTC