From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 3/5] drm/i915: fix VDD override off wait
Date: Fri, 6 Dec 2013 11:47:33 -0800
Message-ID: <20131206114733.24b9d149@jbarnes-desktop>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Fri,  6 Dec 2013 17:32:42 -0200
Paulo Zanoni <przanoni@gmail.com> wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> If we're disabling the VDD override bit and the panel is enabled, we
> don't need to wait for anything. If the panel is disabled, then we
> need to actually wait for panel_power_cycle_delay, not
> panel_power_down_delay, because the power down delay was already
> respected when we disabled the panel.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fe327ce..a2aace2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1142,7 +1142,9 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
>  		/* Make sure sequencer is idle before allowing subsequent activity */
>  		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
>  		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
> -		msleep(intel_dp->panel_power_down_delay);
> +
> +		if ((pp & POWER_TARGET_ON) == 0)
> +			msleep(intel_dp->panel_power_cycle_delay);
>  	}
>  }
>  

Lemme check the eDP docs on this one...  it's supposed to be T12, which
is the time between power cycles.  Yeah that matches what we're using
elsewhere, so:

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center