From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/4] drm/i915: Disable/Enable PM Intrrupts based on the current freq. Date: Mon, 9 Dec 2013 12:11:48 +0200 Message-ID: <20131209101148.GH10036@intel.com> References: <1386492406-24716-1-git-send-email-deepak.s@intel.com> <1386492406-24716-4-git-send-email-deepak.s@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id EEFB7FAEED for ; Mon, 9 Dec 2013 02:12:14 -0800 (PST) Content-Disposition: inline In-Reply-To: <1386492406-24716-4-git-send-email-deepak.s@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Dec 08, 2013 at 02:16:45PM +0530, deepak.s@intel.com wrote: > From: Deepak S > = > When current delay is already at max delay, Let's disable the PM UP > THRESHOLD INTRRUPTS, so that we will not get further interrupts until > current delay is less than max delay, Also request for the PM DOWN > THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and > viceversa for PM DOWN THRESHOLD INTRRUPTS. Are we actually getting these interrupts when we shouldn't? On non-VLV I think GEN6_RP_INTERRUPT_LIMITS should prevent it, but I don't really know about VLV. > = > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 3 files changed, 35 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index a62ac0c..d52a2db 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -915,6 +915,9 @@ struct intel_gen6_power_mgmt { > u8 rp0_delay; > u8 hw_max; > = > + u8 rp_up_masked; > + u8 rp_down_masked; > + > int last_adj; > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 4bde03a..cd82fdd 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -996,7 +996,20 @@ static void gen6_pm_rps_work(struct work_struct *wor= k) > adj *=3D 2; > else > adj =3D 1; > - new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay >=3D dev_priv->rps.max_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | 1 << 5); > + dev_priv->rps.rp_up_masked =3D 1; > + new_delay =3D dev_priv->rps.cur_delay; > + } else > + new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_down_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | ~(1 << 4)); > + dev_priv->rps.rp_down_masked =3D 0; > + } > = > /* > * For better performance, jump directly > @@ -1015,7 +1028,21 @@ static void gen6_pm_rps_work(struct work_struct *w= ork) > adj *=3D 2; > else > adj =3D -1; > - new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay <=3D dev_priv->rps.max_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | 1 << 4); > + dev_priv->rps.rp_down_masked =3D 1; > + new_delay =3D dev_priv->rps.cur_delay; > + } else > + new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_up_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | ~(1 << 5)); > + dev_priv->rps.rp_up_masked =3D 0; > + } > + > } else { /* unknown event */ > new_delay =3D dev_priv->rps.cur_delay; > } > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 716ca24..6b80ec4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4186,6 +4186,9 @@ static void valleyview_enable_rps(struct drm_device= *dev) > vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > dev_priv->rps.rpe_delay); > = > + dev_priv->rps.rp_up_masked =3D 0; > + dev_priv->rps.rp_down_masked =3D 0; > + > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > = > gen6_enable_rps_interrupts(dev); > -- = > 1.8.4.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC