From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes Date: Tue, 10 Dec 2013 14:19:36 +0200 Message-ID: <20131210121936.GN10036@intel.com> References: <1386608057-20866-1-git-send-email-ville.syrjala@linux.intel.com> <20131210125227.1d2bb70f@neptune.home> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 83EB7FB2E6 for ; Tue, 10 Dec 2013 04:19:42 -0800 (PST) Content-Disposition: inline In-Reply-To: <20131210125227.1d2bb70f@neptune.home> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Bruno =?iso-8859-1?Q?Pr=E9mont?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Pr=E9mont wrote: > Hi Ville, > = > On Mon, 09 December 2013 ville.syrjala@linux.intel.com wrote: > > There appear to be some gen2 machines that don't really like the curren= t PLL > > limits we have. We also have some accuracy problems with the PLL calcul= ations. > > This series aims to eliminate those problems, and at least my 855 machi= ne > > seems happier with these patches. > > = > > Ville Syrj=E4l=E4 (5): > > drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel > > drm/i915: Change N divider minimum from 3 to 2 for gen2 > > drm/i915: Increase gen2 vco frequency limit to 1512 MHz > > drm/i915: Fix 66 MHz LVDS SSC freq for gen2 > > drm/i915: Decrease gen2 vco frequency minimum to 908 MHz > > = > > drivers/gpu/drm/i915/intel_bios.c | 8 ++++---- > > drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------= ------ > > 2 files changed, 23 insertions(+), 19 deletions(-) > = > Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and > the PLL debug patch). > = > The WARN() are not hit anymore. > = > [ 46.584578] [drm:intel_dump_pipe_config], DPLL =3D 0x0 > [ 46.584581] [drm:intel_dump_pipe_config], DPLL_MD =3D 0x0 > [ 46.584583] [drm:intel_dump_pipe_config], FP0 =3D 0x0 > [ 46.584586] [drm:intel_dump_pipe_config], FP1 =3D 0x0 OK, so I think the problem got fixed, but my debug patch wasn't all that good since it doesn't dump the values we computed unless the clock is off. Can you still run this (as root) when the LVDS output is active: # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c intel_reg_read is part of intel-gpu-tools. I just want to confirm we calculated the DPLL registers correctly. I know we at least got close since ther WARN is gone, but by my calculations we should get exactly the same as what the BIOS used. -- = Ville Syrj=E4l=E4 Intel OTC