From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Move VLV PHY CRI clock enable into intel_init_dpio() Date: Tue, 10 Dec 2013 20:05:23 +0100 Message-ID: <20131210190523.GL9804@phenom.ffwll.local> References: <1386677205-7316-1-git-send-email-ville.syrjala@linux.intel.com> <20131210105254.43e615cd@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 247C0FAA63 for ; Tue, 10 Dec 2013 11:04:33 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id c41so2425100eek.22 for ; Tue, 10 Dec 2013 11:04:33 -0800 (PST) Content-Disposition: inline In-Reply-To: <20131210105254.43e615cd@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Dec 10, 2013 at 10:52:54AM -0800, Jesse Barnes wrote: > On Tue, 10 Dec 2013 14:06:45 +0200 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > The CRI clock is related to the display PHY, so the setup belongs > > in intel_init_dpio(). > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_display.c | 11 ++++------- > > 1 file changed, 4 insertions(+), 7 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index af3717a..e3ca21f 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1367,6 +1367,10 @@ static void intel_init_dpio(struct drm_device *d= ev) > > if (!IS_VALLEYVIEW(dev)) > > return; > > = > > + /* Enable the CRI clock source so we can get at the display */ > > + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > > + DPLL_INTEGRATED_CRI_CLK_VLV); > > + > > DPIO_PHY_IOSF_PORT(DPIO_PHY0) =3D IOSF_PORT_DPIO; > > /* > > * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - > > @@ -10788,17 +10792,10 @@ static void i915_disable_vga(struct drm_devic= e *dev) > > = > > void intel_modeset_init_hw(struct drm_device *dev) > > { > > - struct drm_i915_private *dev_priv =3D dev->dev_private; > > - > > intel_prepare_ddi(dev); > > = > > intel_init_clock_gating(dev); > > = > > - /* Enable the CRI clock source so we can get at the display */ > > - if (IS_VALLEYVIEW(dev)) > > - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > > - DPLL_INTEGRATED_CRI_CLK_VLV); > > - > > intel_init_dpio(dev); > > = > > mutex_lock(&dev->struct_mutex); > = > Reviewed-by: Jesse Barnes Queued for -next, thanks for the patch. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch