From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 6/8] drm/i915: Rework the FBC interval/stall
 stuff a bit
Date: Thu, 12 Dec 2013 16:03:17 +0100
Message-ID: <20131212150317.GM9804@phenom.ffwll.local>
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To: Imre Deak <imre.deak@intel.com>
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On Thu, Dec 12, 2013 at 04:04:49PM +0200, Imre Deak wrote:
> On Thu, 2013-11-28 at 17:30 +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Don't touch DPFC_RECOMP_CTL on FBC2, use RMW to update
> > the FBC_CONTROL on FBC1 to make it easier for people to
> > experiment with different numbers. Also fix the interval
> > mask for FBC1.
> =

> As I understood the reason for removing DPFC_RECOMP support is that we
> need to understand better how it affects performance etc. before
> enabling it. That's something for the future.
> =

> We could still zero that register in case BIOS leaves there something
> else but that can be done as a follow-up too. So:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

This patch here doesn't really apply on dinq. Ville, can you pls resend?
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch