From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/2] drm/i915: fix DDI PLLs HW state readout code Date: Wed, 8 Jan 2014 17:40:04 +0200 Message-ID: <20140108154004.GK4800@intel.com> References: <1389186748-1954-1-git-send-email-przanoni@gmail.com> <20140108145328.GQ4770@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id F37BBFAB25 for ; Wed, 8 Jan 2014 07:40:08 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140108145328.GQ4770@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 08, 2014 at 03:53:28PM +0100, Daniel Vetter wrote: > On Wed, Jan 08, 2014 at 11:12:27AM -0200, Paulo Zanoni wrote: > > From: Paulo Zanoni > > = > > Properly zero the refcounts and crtc->ddi_pll_set so the previous HW > > state doesn't affect the result of reading the current HW state. > > = > > This fixes WARNs about WRPLL refcount if we have an HDMI monitor on > > HSW and then suspend/resume. > > = > > Cc: stable@vger.kernel.org > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D64379 > > Tested-by: Qingshuai Tian > > Signed-off-by: Paulo Zanoni > > --- > > drivers/gpu/drm/i915/intel_ddi.c | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/in= tel_ddi.c > > index 4ec1665..0def5ef 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -1136,12 +1136,18 @@ void intel_ddi_setup_hw_pll_state(struct drm_de= vice *dev) > > enum pipe pipe; > > struct intel_crtc *intel_crtc; > > = > > + dev_priv->ddi_plls.spll_refcount =3D 0; > > + dev_priv->ddi_plls.wrpll1_refcount =3D 0; > > + dev_priv->ddi_plls.wrpll2_refcount =3D 0; > = > One idea I have for the longer-term is to unify the ddi pll > refcounting/readout stuff with the logic I've created for shared pch plls. > The pch pll sharing checks and refcount logic is now really solid and > completely paranoid with self-checks, and it took about 10 iterations to > get there in a mostly bug-free manner. It looks a bit like ddi pll sharing > is on track to duplicate that, so merging them would be benificial. It > might also help the state pre-computation stuff we still need to do for > plls. We might also want to look into PLL sharing on VLV as well. -- = Ville Syrj=E4l=E4 Intel OTC