From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/vlv: Added/removed Render specific Hw Workarounds for VLV Date: Thu, 9 Jan 2014 18:05:54 +0200 Message-ID: <20140109160554.GM4800@intel.com> References: <1389268309-13555-1-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C7DFFBE95 for ; Thu, 9 Jan 2014 08:06:25 -0800 (PST) Content-Disposition: inline In-Reply-To: <1389268309-13555-1-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 09, 2014 at 05:21:49PM +0530, akash.goel@intel.com wrote: > From: akashgoe > = > The following changes leads to stable behavior, especially > when playing 3D Apps, benchmarks. > = > Added 4 new rendering specific Workarounds > 1. WaTlbInvalidateStoreDataBefore :- > Before pipecontrol with TLB invalidate set, > need 2 store data commands > 2. WaReadAfterWriteHazard :- > Send 8 store dword commands after flush > for read after write hazard > (HSD Gen6 bug_de 3047871) > 3. WaVSThreadDispatchOverride > Performance optimization - Hw will > decide which half slice the thread > will dispatch, May not be really needed > for VLV, as its single slice > 4. WaDisable_RenderCache_OperationalFlush > Operational flush cannot be enabled on > BWG A0 [Errata BWT006] > = > Removed 3 workarounds as not needed for VLV+(B0 onwards) > 1. WaDisableRHWOOptimizationForRenderHang > 2. WaDisableL3CacheAging > 3. WaDisableDopClockGating > = > Modified the implementation of 1 workaround > 1. WaDisableL3Bank2xClockGate > Disabling L3 clock gating- MMIO 940c[25] =3D 1 > = > Modified the programming of 2 registers in render ring init function > 1. GFX_MODE_GEN7 (Enabling TLB invalidate) > 2. MI_MODE (Enabling MI Flush) I posted a bunch of workaround stuff a long time ago. It may have some overlaps with your stuff, and maybe there was something you overlooked. Maybe you could have a look if there's something useful there: http://lists.freedesktop.org/archives/intel-gfx/2013-July/029685.html -- = Ville Syrj=E4l=E4 Intel OTC