* [PATCH] drm/i915/vlv: Add drpc debugfs support for valleyview
@ 2014-01-09 13:58 deepak.s
2014-01-09 16:11 ` Ville Syrjälä
0 siblings, 1 reply; 2+ messages in thread
From: deepak.s @ 2014-01-09 13:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak S
From: Deepak S <deepak.s@intel.com>
Many of the fields from Gen6 have gone away for vlv. Strip all those
fields that are not relevent and try to update fields that we care
about. This patch give information about current RP & RC status and
individual Wells.
Signed-off-by: Deepak S <deepak.s@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 ++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 430eb3e..46f2a9e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1172,6 +1172,51 @@ static int ironlake_drpc_info(struct seq_file *m)
return 0;
}
+static int vlv_drpc_info(struct seq_file *m)
+{
+
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 rpmodectl1, rcctl1;
+ unsigned fw_rendercount = 0, fw_mediacount = 0;
+
+ rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
+ rcctl1 = I915_READ(GEN6_RC_CONTROL);
+
+ seq_printf(m, "Video Turbo Mode: %s\n",
+ yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
+ seq_printf(m, "Turbo enabled: %s\n",
+ yesno(rpmodectl1 & GEN6_RP_ENABLE));
+ seq_printf(m, "HW control enabled: %s\n",
+ yesno(rpmodectl1 & GEN6_RP_ENABLE));
+ seq_printf(m, "SW control enabled: %s\n",
+ yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
+ GEN6_RP_MEDIA_SW_MODE));
+ seq_printf(m, "RC6 Enabled: %s\n",
+ yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
+ GEN6_RC_CTL_EI_MODE(1))));
+ seq_printf(m, "Render Well %s & Media Well : %s\n",
+ (I915_READ(VLV_GTLC_PW_STATUS) &
+ VLV_RENDER_WELL_STATUS_MASK)
+ ? "Up" : "Down",
+ (I915_READ(VLV_GTLC_PW_STATUS) &
+ VLV_MEDIA_WELL_STATUS_MASK)
+ ? "Up" : "Down");
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ fw_rendercount = dev_priv->uncore.fw_rendercount;
+ fw_mediacount = dev_priv->uncore.fw_mediacount;
+ spin_unlock_irq(&dev_priv->uncore.lock);
+
+ seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
+ seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
+
+
+ return 0;
+}
+
+
static int gen6_drpc_info(struct seq_file *m)
{
@@ -1277,7 +1322,9 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
- if (IS_GEN6(dev) || IS_GEN7(dev))
+ if (IS_VALLEYVIEW(dev))
+ return vlv_drpc_info(m);
+ else if (IS_GEN6(dev) || IS_GEN7(dev))
return gen6_drpc_info(m);
else
return ironlake_drpc_info(m);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a699efd..26aab85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4829,6 +4829,9 @@
#define ECOBUS 0xa180
#define FORCEWAKE_MT_ENABLE (1<<5)
+#define VLV_RENDER_WELL_STATUS_MASK 0x80
+#define VLV_MEDIA_WELL_STATUS_MASK 0x20
+
#define GTFIFODBG 0x120000
#define GT_FIFO_SBDROPERR (1<<6)
#define GT_FIFO_BLOBDROPERR (1<<5)
--
1.8.4.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/i915/vlv: Add drpc debugfs support for valleyview
2014-01-09 13:58 [PATCH] drm/i915/vlv: Add drpc debugfs support for valleyview deepak.s
@ 2014-01-09 16:11 ` Ville Syrjälä
0 siblings, 0 replies; 2+ messages in thread
From: Ville Syrjälä @ 2014-01-09 16:11 UTC (permalink / raw)
To: deepak.s; +Cc: intel-gfx
On Thu, Jan 09, 2014 at 07:28:51PM +0530, deepak.s@intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
>
> Many of the fields from Gen6 have gone away for vlv. Strip all those
> fields that are not relevent and try to update fields that we care
> about. This patch give information about current RP & RC status and
> individual Wells.
>
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 49 ++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 430eb3e..46f2a9e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1172,6 +1172,51 @@ static int ironlake_drpc_info(struct seq_file *m)
> return 0;
> }
>
> +static int vlv_drpc_info(struct seq_file *m)
> +{
> +
> + struct drm_info_node *node = (struct drm_info_node *) m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 rpmodectl1, rcctl1;
> + unsigned fw_rendercount = 0, fw_mediacount = 0;
> +
> + rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> + rcctl1 = I915_READ(GEN6_RC_CONTROL);
> +
> + seq_printf(m, "Video Turbo Mode: %s\n",
> + yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
> + seq_printf(m, "Turbo enabled: %s\n",
> + yesno(rpmodectl1 & GEN6_RP_ENABLE));
> + seq_printf(m, "HW control enabled: %s\n",
> + yesno(rpmodectl1 & GEN6_RP_ENABLE));
> + seq_printf(m, "SW control enabled: %s\n",
> + yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
> + GEN6_RP_MEDIA_SW_MODE));
> + seq_printf(m, "RC6 Enabled: %s\n",
> + yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
> + GEN6_RC_CTL_EI_MODE(1))));
> + seq_printf(m, "Render Well %s & Media Well : %s\n",
> + (I915_READ(VLV_GTLC_PW_STATUS) &
> + VLV_RENDER_WELL_STATUS_MASK)
> + ? "Up" : "Down",
> + (I915_READ(VLV_GTLC_PW_STATUS) &
> + VLV_MEDIA_WELL_STATUS_MASK)
> + ? "Up" : "Down");
Why not put these on separate lines?
> +
> + spin_lock_irq(&dev_priv->uncore.lock);
> + fw_rendercount = dev_priv->uncore.fw_rendercount;
> + fw_mediacount = dev_priv->uncore.fw_mediacount;
> + spin_unlock_irq(&dev_priv->uncore.lock);
> +
> + seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
> + seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
> +
> +
> + return 0;
> +}
> +
> +
> static int gen6_drpc_info(struct seq_file *m)
> {
>
> @@ -1277,7 +1322,9 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
> struct drm_info_node *node = (struct drm_info_node *) m->private;
> struct drm_device *dev = node->minor->dev;
>
> - if (IS_GEN6(dev) || IS_GEN7(dev))
> + if (IS_VALLEYVIEW(dev))
> + return vlv_drpc_info(m);
> + else if (IS_GEN6(dev) || IS_GEN7(dev))
> return gen6_drpc_info(m);
> else
> return ironlake_drpc_info(m);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a699efd..26aab85 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4829,6 +4829,9 @@
> #define ECOBUS 0xa180
> #define FORCEWAKE_MT_ENABLE (1<<5)
>
> +#define VLV_RENDER_WELL_STATUS_MASK 0x80
> +#define VLV_MEDIA_WELL_STATUS_MASK 0x20
These should be placed below the relevant register define.
> +
> #define GTFIFODBG 0x120000
> #define GT_FIFO_SBDROPERR (1<<6)
> #define GT_FIFO_BLOBDROPERR (1<<5)
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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2014-01-09 13:58 [PATCH] drm/i915/vlv: Add drpc debugfs support for valleyview deepak.s
2014-01-09 16:11 ` Ville Syrjälä
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